PDF SAA7392 Data sheet ( Hoja de datos )

Número de pieza	SAA7392
Descripción	Channel encoder/decoder CDR60
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA7392 Channel encoder/decoder CDR60 Preliminary speciﬁcation File under Integrated Circuits, IC01 2000 Mar 21 1 page Philips Semiconductors Channel encoder/decoder CDR60 6 PINNING INFORMATION 6.1 Pinning handbook, full pagewidth WREFLO 1 WREFHI 2 WREFMID 3 VSSA1 4 VDDA1 5 WIN 6 VREF 7 IREF 8 n.c. 9 HREFHI 10 HREFLO 11 AGCREF 12 HIN 13 HREFMID 14 VDDA2 15 VSSA2 16 TEST1 17 TEST2 18 VSSD 19 VDDE 20 SAA7392 2000 Mar 21 Fig.2 Pin configuration. 5 Preliminary speciﬁcation SAA7392 60 WCLK 59 DATAO 58 FLAG 57 SYNC 56 EBUOUT 55 V4 54 STOPCK 53 VDDD 52 VSSD 51 PCAin 50 CSi 49 VDDD 48 VSSD 47 ALE 46 RDi 45 WRi 44 VDDE 43 VSSD 42 DA0 41 DA1 MGR792 5 Page This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ADDRESS (HEX) REGISTER NAME 12 Clock Preset Register (ClockPre) 13 Decoder Mode Select Register (DecoMode) 14 Subcode Read End Register (SubReadEnd) 15 Analog Settings Register 1 (AnaSet1) 16 Viterbi Detector Settings Register (VitSet) 17 Tacho Gain Setting Register (Tacho1) 18 Tacho Trip Setting Register (Tacho2) 19 Tacho Control Register (Tacho3) 1B Soft Reset Register (SoftReset) 1D Motor Control Register 7 (Motor7) 1E Input Conﬁguration Register (InputConﬁg) 20 Status Register 2 (Status2) 21 Interrupt Enable Register 2 (IntEn2) 22 Subcode Preset Count Register (SubPresetCount) 23 Subcode Conﬁguration Register 1 (SubConﬁg1) 24 Subcode Conﬁguration Register 2 (SubConﬁg2) 25 Subcode Start Data Register (SubStartData) 26 Subcode Data Register (SubData) 27 Wobble Conﬁguration Register 1 (WobbleConﬁg1) 28 Wobble Conﬁguration Register 2 (WobbleConﬁg2) 29 ATIP Status Register (ATIPStatus) 2A Wobble Frequency Register 1 (WobbleFreq1) 2B Wobble Frequency Register 2 (WobbleFreq2) 2C ATIP Data Register (ATIPData) TYPE FUNCTION BLOCK RESPONSIBLE Write Read Write Clock control Status of Q-channel subcode Decoder mode select clock generator encoder/decoder encoder/decoder Read Read Write Read Q-channel subcode data Subcode data read ﬁnished Analog control C1 frames in FIFO + offset encoder/decoder encoder/decoder analog encoder/decoder Write Write Write Write Write Write Write Read/Write Write Viterbi detector control Tacho gain setting Tacho trip setting Tacho control settings Sub-block reset Control coefﬁcients select EBU clock frequency and input format Interrupt status Enable interrupts bit detector motor/tacho motor/tacho motor/tacho sub-CPU motor/tacho serial input sub-CPU sub-CPU Write Read Write Read/Write Preset count ﬁeld Current count ﬁeld Subcode control Subcode control subcode insert subcode insert subcode insert subcode insert Write Read/Write Subcode control Subcode data Integrator and loop bandwidth Window width ATIP syncs subcode insert subcode insert Wobble processor Wobble processor Write Read Read/Write Read/Write Wobble PLL control ATIP status 8 MSBs of PLL frequency 8 LSBs of PLL frequency Wobble processor Wobble processor Wobble processor Wobble processor Read ATIP data Wobble processor 11 Page

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