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PDF SAA7385 Data sheet ( Hoja de datos )

Número de pieza SAA7385
Descripción Error correction and host interface IC for CD-ROM SEQUOIA
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! SAA7385 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAA7385
Error correction and host interface
IC for CD-ROM (SEQUOIA)
Preliminary specification
File under Integrated Circuits, IC01
1996 Jun 19

1 page




SAA7385 pdf
Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
5 BLOCK DIAGRAM
handbook, full pagewidth
256K × 8 or 1M × 8
DRAM BUFFER
Preliminary specification
SAA7385
CD
DECODER
data subcode
DATA
CONVERTER
AND SUB-CODE
UART
data
subcode
C-flag
BUFFER MANAGER
LAYERED
ERROR
CORRECTOR
BUFFER
MAPPER
53CF94
SCSI
MICROCONTROLLER INTERFACE
SCSI
interface
SERVO
PROCESSOR
S2B serial interface
SAA7385
80C32 MICROCONTROLLER
DEBUG UART
debug
UART
64K × 8 ROM
MGE388
Fig.1 Block diagram (simplified).
6 PINNING
All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25 µA;
Pull-Up = PU25 = 25 µA, PU400 = 400 µA; Slew = S2 = 2 mA, S4 = 4 mA;
CMOS slew = CMOS S2 = CMOS 2 = 2 mA; SCSI pad = SCSI = 48 mA).
SYMBOL PIN I/O
DA2 1 O
DA3 2 O
DA4 3 O
VSS1
DA5
4
5O
DA6 6 O
DA7 7 O
DA8 8 O
DA9 9 O
VDD1
10
PAD
S4
S4
S4
S4
S4
S4
S4
S4
DESCRIPTION
DRAM address bus; bit DA2
DRAM address bus; bit DA3
DRAM address bus; bit DA4
ground 1
DRAM address bus; bit DA5
DRAM address bus; bit DA6
DRAM address bus; bit DA7
DRAM address bus; bit DA8
DRAM address bus; bit DA9
power supply 1
1996 Jun 19
5

5 Page





SAA7385 arduino
Philips Semiconductors
Error correction and host interface IC for
CD-ROM (SEQUOIA)
Preliminary specification
SAA7385
7 FUNCTIONAL DESCRIPTION
7.1 80C32 microcontroller
The standard specification for details of the operation for
this part may be found in any data sheet covering the
80C32 microcontroller. The one deviation from a normal
80C32 is the addition of all of the control registers for the
special function register map for the 80C32. All of the
SAA7385 control registers, including the 53CF94 control
registers appear within this space.
7.2 53CF94 fast SCSI controller
The details of operation of this block may be found in the
“53CF94 data manual”. Two deviations from the operation
of a normal 53CF94 have been made. The first is that the
part supports single-ended SCSI bus operation only.
The second deviation is the additional feature of mapping
the control registers into the 80C32 special function
register map as previously mentioned.
7.4.2 SECTOR SEQUENCER
The sector sequencer de-serializes the data and error
flags from the block decoder and determines when to:
Write data to the buffer
Write flags to the buffer
Test the header to determine the Mode
Test the sub-header to determine the Form
Test the CRC
End the sector and write the status byte to the buffer.
Included in the sector sequencer is the CRC generator
which checks each Yellow Book or Green Book sector as
it is shifted into the SAA7385 in accordance with the
following polynomial:
X32 + X31 + X16 + X15 + X4 + X3 + X + 1
The status of each sector is saved and written to the buffer
at the end of the sector.
7.3 Input clock doubler
To facilitate compatibility of the SAA7385 with the
maximum number of CD decoders, a clock doubler has
been included. This clock doubler may take a
16.9344 MHz clock and double this when requested to do
so by the microcontroller. Logic has been included to
remove the possibility of a ‘runt’ clock pulse when the
doubler is engaged. Once engaged, the only way to
disengage it is via a reset condition.
7.4 Front-end
The front-end is comprised of many sub-sections.
7.4.1 BLOCK DECODER
The block decoder first reverses the bits of each received
byte and then runs them through a linear feedback shift
register to be de-scrambled. The polynomial used to
de-scramble the serial data is as follows: X15 + X + 1
It also detects and tests the synchronization field and will
start the data clock when commanded. The de-scrambled
header is assembled into four registers (MODE, MINS,
SECS and FRMS) with header ready and header error
status (see HDRRDY and HDRERR in RDDSTAT).
The data clock does not have to be enabled to receive
valid headers.
Also included in this section is the logic required to decide
when to start collecting data and sub-code information
taken from the synchronization signal.
7.4.3 SUB-CODE RECEIVE AND Q-CHANNEL EXTRACTOR
A UART which samples asynchronous bits on a 24 clocks
per bit basis is included. This is required because Philips
decoders output the sub-code data at nominally 24 clocks
per bit, but not synchronized to the data. Also included is a
sub-code synchronization detector which senses the
beginning of each new sector of sub-code information.
The serial sub-code information is assembled into bytes in
the following order:
Data bits 7 to 0 = 0, Q, R, S, T, U, V and W.
As each byte is assembled, it is sent to the buffer manager
to be written to the DRAM buffer. At the same time, the
Q-channel bits are assembled into bytes and sent to the
buffer. All Q-channel bytes except CRC are sorted in
registers for use by the microcontroller. The track, mode,
minutes, seconds and frames bytes (RDTK, RDMD,
RDMN, RDSC and RDFM) are also stored in registers for
use by the microcontroller. The Q-channel CRC (last two
bytes) is checked just before the end of the sub-code
sector. If the CRC check fails, BADQ in RDDSTAT is
available to the microcontroller and is written into the buffer
at the end of the sector. When the five Q-channel registers
have been updated, QFRMRDY in RDDSTAT is set.
The five Q-channel registers are valid while QFRMRDY is
set. In the audio mode, HDRRDY in RDDSTAT generates
this interrupt, but the QFRMRDY bit will still be available as
status to the microcontroller.
1996 Jun 19
11

11 Page







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