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PDF SAA7377 Data sheet ( Hoja de datos )
| Número de pieza | SAA7377 | |
| Descripción | Digital servo processor and Compact Disc decoder CD7 | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7377
Digital servo processor and
Compact Disc decoder (CD7)
Product specifications
File under Integrated Circuits, IC01
1998 Jul 06
1 page  
Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
6 PINNING
SYMBOL
VSSA1
VDDA1
D1
D2
D3
VRL
D4
R1
R2
IrefT
VRH
VSSA2
SELPLL
ISLICE
HFIN
VSSA3
HFREF
Iref
VDDA2
TEST1
CRIN
CROUT
TEST2
CL16
CL11
RA
FO
SL
TEST3
VDDD1(P)
DOBM
VSSD1
MOTO1
MOTO2
SBSY
SFSY
RCK
SUB
VSSD2
V5
1998 Jul 06
PIN
1(1)
2(1)
3
4
5
6
7
8
9
10
11
12(1)
13
14
15
16(1)
17
18
19(1)
20
21
22
23
24
25
26
27
28
29
30(1)
31
32(1)
33
34
35
36
37
38
39(1)
40
DESCRIPTION
analog ground 1
analog supply voltage 1
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
reference voltage input for ADC
unipolar current input (central diode signal input)
unipolar current input (satellite diode signal input)
unipolar current input (satellite diode signal input)
current reference output for ADC calibration
reference voltage output from ADC
analog ground 2
selects whether internal clock multiplier PLL is used
current feedback output from data slicer
comparator signal input
analog ground 3
comparator common mode input
reference current output pin (nominally 0.5VDD)
analog supply voltage 2
test control input 1; this pin should be tied LOW
crystal/resonator input
crystal/resonator output
test control input 2; this pin should be tied LOW
16.9344 MHz system clock output
11.2896 or 5.6448 MHz clock output (3-state)
radial actuator output
focus actuator output
sledge control output
test control input 3; this pin should be tied LOW
digital supply voltage 1 for periphery
bi-phase mark output (externally buffered; 3-state)
digital ground 1
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
subcode block sync output (3-state)
subcode frame sync output (3-state)
subcode clock input
P-to-W subcode output bits (3-state)
digital ground 2
versatile output pin 5
5
Product specifications
SAA7377
5 Page 
Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specifications
SAA7377
7.5 Subcode data processing
7.5.1 Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal
buffer. The last 16 bits are used internally to perform a
Cyclic Redundancy Check (CRC). If the data is good, the
SUBQREADY-I signal will go LOW. SUBQREADY-I can
be read via the SDA or STATUS pins, selected via
register 2. Good Q-channel data may be read from SDA.
7.5.2
EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACES
Data from all the subcode channels (P-to-W) may be read
via the subcode interface, which conforms to
EIAJ CP-2401. The interface is enabled and configured as
either a 3-wire or 4-wire interface via register F. The
subcode interface output formats are illustrated in Fig.7,
where the RCK signal is supplied by another device such
as a CD graphics decoder.
7.5.3 V4 SUBCODE INTERFACE
Data of subcode channels, Q-to-W, may be read via pin V4
if selected via register D. The format is similar to RS232
and is illustrated in Fig.8. The subcode sync word is
formed by a pause of 200 µs minimum. Each subcode byte
starts with a logic 1 followed by 7 bits (Q-to-W). The gap
between bytes is variable between 11.3 µs and 90 µs.
The subcode data is also available in the EBU output
(DOBM) in a similar format.
handbook, full pagewidth
SBSY
SFSY
RCK
SUB
SFSY
RCK
SUB
SF0 SF1 SF2 SF3
SF97
SF0
P-W
P-W
P-W
EIAJ 4-wire subcode interface
SF0 SF1 SF2 SF3
SF97
SF0
SFSY
RCK
SUB
P-W
P-W
P-W
EIAJ 3-wire subcode interface
P QR S T U VW
SF1
SF1
MBG410
1998 Jul 06
Fig.7 EIAJ subcode (CD graphics) interface format.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7377.PDF ] | |
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