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PDF SAA7374 Data sheet ( Hoja de datos )

Número de pieza SAA7374
Descripción Low voltage digital servo processor and Compact Disc decoder CD7LV
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! SAA7374 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAA7374
Low voltage digital servo processor
and Compact Disc decoder
(CD7LV)
Product specification
Supersedes data of 1995 Dec 06
File under Integrated Circuits, IC01
1998 Feb 26

1 page




SAA7374 pdf
Philips Semiconductors
Low voltage digital servo processor and
Compact Disc decoder (CD7LV)
6 PINNING
SYMBOL
VSSA1
VDDA1
D1
D2
D3
VRL
D4
R1
R2
IrefT
VRH
VSSA2
SELPLL
ISLICE
HFIN
VSSA3
HFREF
Iref
VDDA2
TEST1
CRIN
CROUT
TEST2
CL16
CL11
RA
FO
SL
TEST3
VDDD1(P)
DOBM
VSSD1
MOTO1
MOTO2
SBSY
SFSY
RCK
SUB
VSSD2
V5
1998 Feb 26
PIN
1(1)
2(1)
3
4
5
6
7
8
9
10
11
12(1)
13
14
15
16(1)
17
18
19(1)
20
21
22
23
24
25
26
27
28
29
30(1)
31
32(1)
33
34
35
36
37
38
39(1)
40
DESCRIPTION
analog ground 1
analog supply voltage 1
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
unipolar current input (central diode signal input)
reference voltage input for ADC
unipolar current input (central diode signal input)
unipolar current input (satellite diode signal input)
unipolar current input (satellite diode signal input)
current reference output for ADC calibration
reference voltage output from ADC
analog ground 2
selects whether internal clock multiplier PLL is used
current feedback output from data slicer
comparator signal input
analog ground 3
comparator common mode input
reference current output pin (nominally 0.5VDD)
analog supply voltage 2
test control input 1; this pin should be tied LOW
crystal/resonator input
crystal/resonator output
test control input 2; this pin should be tied LOW
16.9344 MHz system clock output
11.2896 or 5.6448MHz clock output (3-state)
radial actuator output
focus actuator output
sledge control output
test control input 3; this pin should be tied LOW
digital supply voltage 1 for periphery
bi-phase mark output (externally buffered; 3-state)
digital ground 1
motor output 1; versatile (3-state)
motor output 2; versatile (3-state)
subcode block sync output (3-state)
subcode frame sync output (3-state)
subcode clock input
P-to-W subcode bits output (3-state)
digital ground 2
versatile output pin 5
5
Product specification
SAA7374

5 Page





SAA7374 arduino
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SUBCODE
PROCESSOR
output from
data slicer
DIGITAL PLL AND
DEMODULATOR
FIFO
ERROR
CORRECTOR
1
V4
0
0 : reg D = xx01
V4 SUBCODE
INTERFACE
CD GRAPHICS
INTERFACE
reg F
SBSY
SFSY
SUB
MICROCONTROLLER
INTERFACE
SDA
1 : reg A = xx0x
0 : reg A = xx1x
1
0
1 : reg 3 = xx10
(1fs mode)
0 : reg 3 xx10
FADE/MUTE/
INTERPOLATE
1 PHASE
DIGITAL 0 COMPENSATION
FILTER
reg 3
KILL
KILL
V3
reg C
DE-EMPHASIS
FILTER
EBU
INTERFACE
reg A
DOBM
1 : no pre-emphasis detected
OR reg D = 01xx (de-emphasis signal at V5)
0 : pre-emphasis detected
AND reg D 01xx
1
0
1
0
1
0
I2S-BUS
INTERFACE
SCLK
WCLK
DATA
EF
1 : reg 3 101x
reg 3
0 : reg 3 = 101x
(CD-ROM modes)
MBG418
Fig.6 Simplified data flow of decoder functions.

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