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PDF SAA7360 Data sheet ( Hoja de datos )
| Número de pieza | SAA7360 | |
| Descripción | Bitstream conversion ADC for digital audio systems | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7360
Bitstream conversion ADC
for digital audio systems
Product specification
Supersedes data of July 1993
File under Integrated Circuits, IC01
Philips Semiconductors
1995 Apr 24
1 page  
Philips Semiconductors
Bitstream conversion ADC
for digital audio systems
Product specification
SAA7360
SYMBOL
HPEN
TSEL
WSEL
ODF2 and
ODF1
RESET
CEN
PIN DESCRIPTION
38 high-pass filter enable input (HPEN = HIGH = enabled); if unconnected this pin defaults
HIGH
39 input to select master (TSEL = LOW) or slave (TSEL = HIGH) operation of the serial
interface; if unconnected this pin defaults HIGH
40 input to indicate 16-bit (WSEL = HIGH) or 18-bit (WSEL = LOW) output data word length of
the serial interface; if unconnected this pin defaults HIGH
41 and 42 serial interface format inputs; these 2 pins determine the interface format in which the device
will operate (see Chapter “Functional Description”); if unconnected these pins will default
HIGH (I2S format)
43 Power-On Reset (POR) input (active LOW) to mute the digital output during power on
44 Chip enable input; this pin, when LOW, disables the operation of the device and 3-states the
outputs of the serial interface bus. This enables the connection of one of more devices to the
output bus; if unconnected this pin defaults HIGH.
handbook, full pagewidth
FSEL 1
TEST1 2
TEST2 3
VSSD 4
VDDD 5
XIN 6
XOUT 7
XSYS1 8
XSYS2 9
SCKI 10
SCKO 11
SAA7360
33 PINL
32 NINL
31 BAOL
30 BAIL
29 VDACP
28 Iref
27 VDACN
26 BAIR
25 BAOR
24 NINR
23 PINR
MLA715 - 2
1995 Apr 24
Fig.2 Pin configuration.
5
5 Page 
Philips Semiconductors
Bitstream conversion ADC
for digital audio systems
Product specification
SAA7360
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog part
VOLTAGE REFERENCE VrefL AND VrefR
VI input voltage
Current reference Iref (note 11)
IO output current
2.0 2.3
2.7
−
1--V--3--r--e-k--f-ΩR---
−
V
A
DAC reference
INPUT VDACN
VI input voltage
INPUT VDACP
VI input voltage
−
VSSA
−
−
VDDA
−
V
V
Sigma-Delta modulator inputs PINR, NINR, PINL and NINL
VI(rms)
input voltage (RMS value)
note 12
−1 − V
ADC performance (note 13)
THD + N
DR
αcs
G
tgd
total harmonic
distortion + noise
dynamic range
channel separation
gain
group delay (in pass band)
at −1 dB digital output; −
note 14
note 14
93
fi = 1 kHz; note 15
−
−1.5
note 16
−
−90
(0.003%)
97
100
−1
1.25
−85
(0.0056%)
−
−
−0.5
−
dB
dB
dB
dB
ms
Notes
1. Minimum VIL, VOL and maximum VIH, VOH are peak values to allow for transients.
2. ILI minimum and ILO minimum measured at VI = 0 V; ILI maximum and ILO maximum measured at VI = VDDD.
3. fxtal is a multiple of the system sampling frequency fs which can vary between 18 and 53 kHz.
4. Output times are measured with a capacitive load of 35 pF; XSYS2 is the master clock frequency divided by 2.
5. tH valid only when used with XTAL, with 50% input mark space ratio; XSYS1 (tH) is measured at 1⁄2VDDD.
6. Output times are measured with a capacitive load of 20 pF.
7. Output times are measured with a capacitive load of 50 pF.
8. Relative to SCKO in master mode.
9. In slave mode the number of SCKI clocks in each channel should be <33 and the same in both. The polarity of SWSI
indicates left/right channel.
10. Relative to SCKI in slave mode.
11. Iref connected to 0 V via a 13 kΩ resistor.
12. The maximum recommended input voltage (referred to as 0 dB) yields a −1 dB output (relative to full-scale digital
swing). The input voltage scales with V(VDACP) − V(VDACN); almost equal to VDDA, hence:
VI (0 dB) = --[--V------(--V----D----A---C----P---)-----5–----V------(--V-----D---A----C---N----)---]- V (RMS value)
13. Device measured with external components as shown in recommended application diagram (see Fig.7).
1995 Apr 24
11
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| PDF Descargar | [ Datasheet SAA7360.PDF ] | |
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