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PDF SAA7348GP Data sheet ( Hoja de datos )

Número de pieza SAA7348GP
Descripción All Compact Disc Engine ACE
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
DATA SHEET
SAA7348GP
All Compact Disc Engine (ACE)
Preliminary specification
File under Integrated Circuits, IC22
1997 Jul 11

1 page




SAA7348GP pdf
Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
5 BLOCK DIAGRAM
handbook, full pagewidth
VSSA
VSSD
SBSY RCK
VALID DATA SCLK
KILL
VDDA VDDD(core) VDDD(pads) SFSY SUB
DAC WCLK DACCLK DEEM
22 2 9
3
(1) (2) (3) (4) (5)
92 93 94 95 65 66 67 68 69 62 97 96
MIDLAD
REFLCA
HFIN
REFHCA
Iref
7
8
9 HF
10 FRONT-END
11
DECODER
89
71
73
72
91
86
85
SAA7348GP
VRH
D1
D2
D3
D4
S1
S2
IrefT
FTCH
FTCL
14
15
16
17
20
21 LF
22 FRONT-END
23
24
25
DIGITAL SERVO
84
83
82
74
75
78
79
80
90
98
99
100
XTALI
XTALO
SELPLL
28
27
26
CLOCK
PLL
80C51
5
6
DOBM
SUBQW
MOTOV
MOTOS
FB
C2FAIL
CFLG
FOK
TL
RP
DSDEN
CLO
RA
FO
SL
OTD
DEFI
DEFO
LDON
TPWM
TEN
TEST
123
(1) Pins 13 and 19.
(2) Pins 12 and 18.
TS1
TS3
(3) Pins 39 and 88.
TS2
(4) Pins 29, 38, 51, 61,
63, 70, 76, 81 and
87.
(5) Pins 52, 64 and 77.
30 31 32 33 34 35 36 37
8
40 to
47
8
53 to
60 48 49 50
RXD0 INT0
RXD1
WR
A8 to AD0 to
ALE
TXD0 INT1
TXD1
RD A15 AD7 PSEN
EA
Fig.1 Block diagram.
MGK498
1997 Jul 11
5

5 Page





SAA7348GP arduino
Philips Semiconductors
All Compact Disc Engine (ACE)
Preliminary specification
SAA7348GP
Table 1 Typical input currents for a range of values of RIrefT
RIrefT
(k)
200
220
240
270
300
330
360
390
430
470
510
560
620
680
750
TYPICAL CURRENT INPUT RANGE
fsys(1) = 4.2336 MHz
fsys(1) = 8.4672 MHz
D1, D2, D3, D4
(µA)
S1, S2
(µA)
VRH
D1, D2, D3, D4
S1, S2
(V) (µA) (µA)
12.000
10.909
10.000
8.889
8.000
7.273
6.667
6.154
5.581
5.106
4.706
4.286
3.871
3.529
3.200
6.000
5.455
5.000
4.444
4.000
3.636
3.333
3.077
2.791
2.553
2.353
2.143
1.935
1.765
1.600
1.891
1.719
1.576
1.396
1.261
1.146
1.051
0.970
0.880
0.805
0.742
0.675
0.610
0.556
0.504
12.000
10.909
10.000
8.889
8.000
7.273
6.667
6.350
6.000
5.455
5.000
4.444
4.000
3.636
3.333
3.175
Note
1. fsys is always equal to s----e---r--v---o---2----c---l-o---c---k-- ; see Table 9.
VRH
(V)
0.946
0.860
0.788
0.698
0.631
0.573
0.526
0.500
The preset latch command can be used to select this
method of VRH automatic adjustment.
Alternatively, the dynamic range of the input currents can
be made dependent on the ADC reference voltage, VRH.
In this case, the maximum input current for the central and
satellite diodes, respectively, is:
Ii(central) (max) = fsys × VRH × 1.10 × 106 ( µA)
Ii(satellite) (max) = fsys × VRH × 0.55 × 106 ( µA)
where fsys = 4.2336 MHz.
VRH can be set to any one of 32 pre-defined levels,
selectable under software control. VRH is initially set to
2.5 V using the preset latch command, then incremented
or decremented one level at a time by repeatedly
resending the same commend.
7.2 Decoder functions
The SAA7348 is a multi-speed decoding device with an
internal phase locked loop clock multiplier. Several
playback speeds can be selected, depending on the
crystal frequency and the internal clock settings;
see Table 2.
The following functions are performed in the decoder
block:
Demodulation (includes sync protection circuit);
converts the 14-bit EFM data and subcode words into
8-bit symbols.
Subcode data processing.
Error correction; a t = 2, e = 4 type is used on both C1
(32 symbol) and C2 (28 symbol) frames. The error
corrector can correct up to 2 errors on the C1 level and
up to 4 errors on the C2 level. The error corrector also
contains a flag processor. Flags are assigned to
symbols when the error corrector cannot ascertain if the
symbols are definitely good. C1 generates output flags
that are used by C2. The C2 output flags are used by the
interpolator to conceal uncorrectable errors for audio
output; they are also output via the EBU signal (DOBM)
and the VALID output with I2S for CD-ROM applications.
1997 Jul 11
11

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