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PDF SAA7325 Data sheet ( Hoja de datos )

Número de pieza SAA7325
Descripción Digital servo processor and Compact Disc decoder with integrated DAC CD10
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! SAA7325 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAA7325
Digital servo processor and
Compact Disc decoder with
integrated DAC (CD10)
Product specification
File under Integrated Circuits, IC01
1999 Jun 17

1 page




SAA7325 pdf
Philips Semiconductors
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10)
5 BLOCK DIAGRAM
Product specification
SAA7325
handbook, full pagewidth
D1 D2 D3 D4
8 9 10 11
VSSA2
VDDA2
VSSD2 VDDD1(P)
VSSA1
VDDA1
VSSD1
VSSD3 VDDD2(C)
4 14 5 17 33 50 58 52 57
R1 12
R2 13
ADC
PRE-
PROCESSING
VRIN
7
SCL
SDA
RAB
SILD
40
39
41
42
Vref
GENERATOR
MICROCONTROLLER
INTERFACE
HFIN
HFREF
ISLICE
Iref
2
1
3
6
FRONT-END
TEST1
TEST2
TEST3
25
31
44
TEST
DIGITAL
PLL
EFM
DEMODULATOR
SRAM
CONTROL
FUNCTION
CONTROL
PART
SAA7325
OUTPUT
STAGES
MOTOR
CONTROL
54
RA
55
FO
56
SL
64
LDON
59
MOTO1
60
MOTO2
ERROR
CORRECTOR
FLAGS
53
CFLG
AUDIO
PROCESSOR
EBU
INTERFACE
51
DOBM
SELPLL
CRIN
CROUT
CL16
CL11/4
24
16
15
26
49
SBSY
SFSY
SUB
RCK
48
47
46
45
STATUS
43
RESET
38
TIMING
DECODER
MICRO-
CONTROLLER
INTERFACE
RAM
ADDRESSER
SUBCODE
PROCESSOR
PEAK
DETECT
VERSATILE PINS
INTERFACE
63 34 61 62
V1 V2/V3 V4 V5
KILL
32
KILL
SERIAL DATA
INTERFACE
30
29
28
27
SERIAL DATA
(LOOPBACK)
INTERFACE
37
35
36
BITSTREAM
DAC
20
21
18
19
22
23
EF
SCLK
WCLK
DATA
SCLI
WCLI
SDI
Vneg
Vpos
LN
LP
RN
RP
MGL681
Fig.1 Block diagram.
1999 Jun 17
5

5 Page





SAA7325 arduino
Philips Semiconductors
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10)
Product specification
SAA7325
100 nF
VSSA
HF input
1 nF
47 pF
2.2 k
HFREF
HFIN
22 k
100 nF
VSSA
ISLICE
crystal
clock
DQ
100 µA
100 µA
VSS
VDD
DPLL
MGS179
Fig.6 Data slicer showing typical application components.
7.4 Demodulator
7.4.1 FRAME SYNC PROTECTION
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
A sync coincidence is detected; sync pattern occurs
588 ±1 EFM clocks after the previous sync pattern
A new sync pattern is detected within ±6 EFM clocks of
its expected position.
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence found, and reset LOW if during 61
consecutive frames no sync coincidence is found. The PLL
lock signal can be accessed via the SDA or STATUS pins
selected by decoder registers 2 and 7.
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2 EFM DEMODULATION
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
1999 Jun 17
11

11 Page







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