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PDF SAA7240HS Data sheet ( Hoja de datos )
| Número de pieza | SAA7240HS | |
| Descripción | MPEG-2 Transport RISC processor | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7240
MPEG-2 Transport RISC processor
Product specification
File under Integrated Circuits, IC02
2001 Oct 22
1 page  
Philips Semiconductors
MPEG-2 Transport RISC processor
Product specification
SAA7240
2 GENERAL DESCRIPTION
The SAA7240 is a transport MPEG-2 source decoder
designed for application in set-top boxes in a Digital Video
Broadcast (DVB) environment. It is targeted to BSkyB 3.00
and Canal+ basic box and web box applications. The
device is part of a comprehensive source decoding kit that
contains all the hardware and software required to receive
and decode MPEG-2 transport streams, including
descrambling and demultiplexing.
In addition, it includes a PR3930 core, which is a 32-bit
MIPS RISC-based CPU core supporting the MIPS16
instruction set (to reduce memory requirements) and
several peripheral interfaces such as UARTs, I2C-bus
units, an IEC 1883, and an IEEE 1284 (Centronics)
interface. The SAA7240 is therefore capable of performing
all controller tasks in digital television applications.
Furthermore, the SAA7240 complies with DVB, ICAM and
MULTI2 descrambler standards.
The SAA7240 receives transport streams through a
versatile stream input interface capable of handling both
byte-parallel and bit-serial streams, in various formats,
supporting data streams up to and including 13.5 Mbytes/s
in parallel mode and 81 Mbits/s in serial mode. The data
stream is first applied to an on-chip descrambler with a
DVB descrambling algorithm, on the basis of 14 control
word pairs stored in an on-chip RAM.
Demultiplexing is subsequently applied to the data stream,
to separate up to 40 individual data streams. The
demultiplexer section includes clock recovery and
timebase management. Program Specific Information
(PSI), Service Information (SI), Conditional Access (CA)
messages and private data are selected and stored in
external memory, for subsequent off-line processing by
the internal PR3930 CPU core.
To support advanced board testing facilities, the SAA7240
includes Boundary Scan Test (BST) hardware, according
to the JTAG standard. The device features flexible
low-power Sleep modes, which independently control the
activity of each functional block and can sustain set-top
box standby functionality, thus eliminating the need for a
separate front-panel controller.
The SAA7240 requires a supply voltage of 3.3 V for the
I/O pads and a supply voltage of 2.5 V for the core.
2.1 Limitation notes
Although the most advanced techniques and sophisticated
tools are used during the design and validation phases,
some design limitations giving some restrictions for
specific applications might be discovered during the
characterization of the SAA7240 and during its life time.
If such an eventuality occurs, a limitation note will be
issued, describing the deviation against the specification
and the advised work-around if any. This limitation note,
also sometimes called ‘anomaly sheet’ or ‘bug list’, is given
to customers when they are in the initial design-in phase.
Once the design-in is in production phase, customers are
informed about any new limitation if the severity is
estimated to be high.
Please contact your nearest Philips Semiconductor sales
office for more information.
2.2 Integrated Conditional Access Module (ICAM®)
licensing requirements
Companies planning to use ICAM® implementation in any
final product must obtain a license from News Data
System Corporation before designing such products.
Additional per-chip royalties may be required and are to be
paid by the purchaser to News Data System Corporation.
For information on the Integrated Conditional Access
Module features, a non-disclosure agreement must be
signed with Philips Semiconductors to get the ICAM®
specification.
Please contact your nearest Philips Semiconductor sales
office for more information.
3 ORDERING INFORMATION
TYPE NUMBER
SAA7240
NAME
SQFP208
PACKAGE
DESCRIPTION
plastic shrink quad flat package, 208 leads (lead length 1.3 mm);
body 28 × 28 × 34 mm; high stand-off height
VERSION
SOT316-1
2001 Oct 22
5
5 Page 
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SYMBOL
I2C-bus 0 interface
SDA0
PIN
150
TYPE
I/O data line
DESCRIPTION
SCL0
149 I/O clock line
I2C-bus 1 interface
SDA1
148
I/O data line
SCL1
147 I/O clock line
Smart card 0 interface
SC_I/O0
134
I/O I/O line
CLK_CARD0
128
CMDVCCN0
129
RSTIN0
132
OFFN0
133
Smart card 1 interface
SC_I/O1
126
O clock to the card
O command of the card power supply
O reset of the card
I card presence detection
I/O I/O line
CLK_CARD1 122 O clock to the card
CMDVCCN1
123 O command of the card power supply
RSTIN1
124 O reset of the card
OFFN1
125 I card presence detection
Parallel or serial transport input interface from the front-end
PKTDATA[0:7]
164 to 157 I 8-bit primary TS data input
PKTSTROBE 154 I/O byte strobe or bit strobe
PKTVALID
PKTSYNC
156 I data valid or bit stream word select
155 I packet synchronization
BUFFER TYPE
RESET
STATE
bidirectional; CMOS input;
open-drain; 8 mA output drive
bidirectional; CMOS input;
open-drain; 8 mA output drive
Z
Z
bidirectional; CMOS input;
open-drain; 8 mA output drive
bidirectional; CMOS input;
open-drain; 8 mA output drive
Z
Z
bidirectional; CMOS input;
open-drain; 8 mA output drive
2 mA output drive
2 mA output drive
2 mA output drive
CMOS input
Z
LOW
HIGH
HIGH
Z
bidirectional; CMOS input;
open-drain; 8 mA output drive
2 mA output drive
2 mA output drive
2 mA output drive
CMOS input
Z
LOW
HIGH
HIGH
Z
CMOS input
bidirectional; CMOS input;
2 mA output drive
CMOS input
Z
Z
Z
Z
11 Page | ||
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