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PDF SAA7219 Data sheet ( Hoja de datos )

Número de pieza SAA7219
Descripción MPEG2 Transport RISC processor
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! SAA7219 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
SAA7219
MPEG2 Transport RISC processor
Preliminary specification
File under Integrated Circuits, IC02
1999 Sep 20

1 page




SAA7219 pdf
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CPU section
MIPS
PR3930
CORE
DATA CACHE
INSTRUCTION CACHE
TIMER 1
TIMER 2
TIMER 3 (WATCHDOG)
DSU
EJTAG
MMU
input
stream
output
stream
PWM
demultiplexer descrambler section
INPUT
INTERFACE
PID
FILTER
DESCRAMBLER
DVB AND MULTI2
MPEG system-bus
AV
FILTER
AUDIO AND
VIDEO
INTERFACE
GP/HS
INTERFACE
1394 GATEWAY
PCR
TS/PES
PROCESSING FILTERS
SECTION
FILTERS
MPEG SYSTEM
GATEWAY
FILTER DMA
CONTROLLER
M
MPEG SYSTEM
INT.HANDLER
PI-bus
AVD
interface
Reset
Clock
SS
PI-BUS EXTENSION BUS
CTRL CONTROLLER
M
CARD READER
01
MM
S
UART
SSI
2 01
PIO
INTERFACE
S
I2C
01
M
1284
S
RTC
32 KHz
S
INTERRUPT
CONTROLLER
S
4-KBYTE
SRAM
JTAG
peripheral section
JTAG interface external
bus interface
smart card
interface
UART and SSI
connections
32-bit PIO SCL and 1284 bus
SDA lines
M = master peripheral with embedded DMA channel
S = slave peripheral
FCE374
Fig.1 Block diagram.

5 Page





SAA7219 arduino
SYMBOL
PIN
JTAG and Test interface (5 pins)
TDO
178
I/O BUFFER TYPE
O 3-state, 2 mA output drive
TDI 179 I TTL input
TMS
180 I TTL input
TRST
181 I TTL input
TCK
184 I TTL input
EJTAG extension reserved for PR3930 (4 pins)
DSU_CLK 185 O 2 mA output drive
PCST0 to PCST2
186, 188, 189
O 2 mA output drive
VOLT(1)
DESCRIPTION
3.3 V
5V
5V
5V
5V
Test data output/Target PC output.
Real-Time Trace mode off. Serial output data is
shifted from JTAG instruction register to the TDO
pin at the falling of the TCK clock. When no data is
shifted out, TDO is 3-stated.
Real-Time Trace mode on. TDO provides
non-sequential program counter output at the
processor clock speed.
Test data input/Debug interrupt.
Real-Time Trace mode off. Serial input data (TDI) is
shifted into the JTAG instruction register or data
register on the rising edge of the TCK clock,
depending of the TAP controller state.
Real-Time Trace mode on. An active LOW level at
this input sampled by TCK positive edge, is used as
interrupt to switch the Real-Time Trace mode off
(standard JTAG).
Test mode select. This input is decoded by the TAP
controller to control test operation. Sampled on
TCK rising edge.
Test reset. Active LOW level for asynchronous reset
of the EJTAG module, independent of the processor
logic.
Test clock. Input clock used to shift data into or out
the JTAG instruction or data register.
3.3 V
3.3 V
DSU clock is equivalent to the processor clock.
Captures address and data from pin TDO when PC
trace mode is on. Is 3-stated when bit 0 or 15 of the
JTAG Control Register is logic 0.
CPU status: debug mode, pipeline stall, occurrence
of exception

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