PDF SAA7191B Data sheet ( Hoja de datos )

Número de pieza	SAA7191B
Descripción	Digital Multistandard Colour Decoder/ Square Pixel DMSD-SQP
Fabricantes	NXP Semiconductors
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INTEGRATED CIRCUITS DATA SHEET SAA7191B Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Product speciﬁcation File under Integrated Circuits, IC22 August 1996 1 page Philips Semiconductors Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Product speciﬁcation SAA7191B 6 PINNING SYMBOL SP AP RESN CREF VDD1 CHR0 CHR1 CHR2 CHR3 CHR4 CHR5 CHR6 CHR7 CVBS0 CVBS1 CVBS2 CVBS3 VDD2 VSS1 CVBS4 CVBS5 CVBS6 CVBS7 GPSW1 GPSW2 HCL LLC VDD3 HSY VS HS HL XTAL XTALI VSSA LFCO VDDA VSS2 ODD SDA PIN DESCRIPTION 1 connected to ground (shift pin for testing) 2 connected to ground (action pin for testing) 3 reset, active LOW 4 clock reference, sync from external to ensure in-phase signals on the YUV-bus 5 +5 V supply input 1 6 7 8 9 chrominance input data bits CHR7 to CHR0 10 from a Y/C (VHS, Hi8) source in two’s complement format 11 12 13 14 15 luminance respectively CVBS lower input data bits CVBS3 to CVBS0 16 (CVBS with luminance, chrominance and all sync information in two’s complement format) 17 18 +5 V supply input 2 19 ground 1 (0 V) 20 21 luminance respectively CVBS upper input data bits CVBS7 to CVBS4 22 (CVBS with luminance, chrominance and all sync information in two’s complement format) 23 24 Port 1 output for general purpose (programmable) 25 Port 2 output for general purpose (programmable) 26 black level clamp pulse (programmable), e.g. for TDA8708 (ADC) 27 line-locked clock input signal (29.5 MHz for 50 Hz system; 24.5454 MHz for 60 Hz system) 28 +5 V supply input 3 29 horizontal sync indicator output signal (programmable), e.g. for TDA8708 (ADC) 30 vertical sync output signal 31 horizontal sync output signal (programmable) 32 horizontal lock ﬂag, HIGH = PLL locked 33 26.8 MHz clock output 34 26.8 MHz connection for crystal or external oscillator (TTL compatible squarewave) 35 analog ground 36 line frequency control output signal, multiple of horizontal frequency (7.375 MHz/6.136363 MHz) 37 +5 V supply input for analog part 38 ground 2 (0 V) 39 odd/even ﬁeld identiﬁcation output (odd = HIGH); active only at NFEN-bit = 1 40 I2C-bus data line August 1996 5 5 Page Philips Semiconductors Digital Multistandard Colour Decoder, Square Pixel (DMSD-SQP) Product speciﬁcation SAA7191B 7.2 Luminance processor The luminance input signal, a digital CVBS format or an 8-bit luminance format (S-VHS, Hi8), is fed through a sample rate converter to reduce the data rate to 14.75 MHz for PAL and SECAM (12.2727 MHz for NTSC), Fig.4. Sample rate is converted by means of a switchable pre-filter. High frequency components are emphasized to compensate for loss in the following chrominance trap filter. This chrominance trap filter (fo = 4.43 MHz or fo = 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be by-passed for S-Video (S-VHS and Hi8) signals. The high frequency components of the luminance signal can be “peaked” (control for sharpness improvement via the I2C-bus) in two bandpass filters with selectable transfer characteristic. A coring circuit with selectable characteristic improves the signal once more, this signal is then added to the original (“unpeaked”) signal. A switchable amplifier achieves a common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed to the variable delay compensation. 7.3 Processing delay The delay from input to output is 220 LLC cycles if YDEL is set to 0. The processing delay will be influenced in future enhancements. 7.4 Synchronization The luminance output signal is fed to the synchronization stage. Its bandwidth is reduced to 1 MHz in a low-pass filter. The sync pulses are sliced and fed to the phase detectors to be compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Adjustable output signals (e. g. HCL and HSY) are generated according to peripheral requirements (TDA8708A, TDA8709A). The output signals HS, VS and PLIN are locked to the timing reference signal HREF (Figures 7 and 8). There is no absolute timing reference guaranteed between the input signal and the HREF signal as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications, which ask for absolute timing accuracy to the input signals. The loop filter signal drives an oscillator to generate the line frequency control output signal LFCO. Table 1 Clock frequencies in MHz for 50/60 Hz systems CLOCK LLC LLC2 LLC4 LLC8 50 Hz 29.5 14.75 7.375 3.6875 60 Hz 24.545454 12.272727 6.136136 3.068181 7.5 Line locked clock frequency LFCO is required in an external PLL (SAA7197) to generate the line locked clock frequency. 7.6 YUV-bus, digital outputs The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or to the digital-to-analog converter (DAC). Outputs are controlled via the I2C-bus in normal selections, or they are controlled by output enable chain (FEIN on pin 64, Fig.5). The YUV-bus data rate equals LLC2 in Table 1. Timing is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference). YUV-bus formats 4:2:2 and 4:1:1 The output signals Y7 to Y0 are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits of the multiplexed colour-difference signals (B−Y) and (R−Y). The frame in the following tables is the time, required to transfer a full set of samples. In case of 4 : 2 : 2 format two luminance samples are transmitted in comparison to one U and one V sample within one frame. August 1996 11 11 Page

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