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PDF SAA7146AHZ Data sheet ( Hoja de datos )
| Número de pieza | SAA7146AHZ | |
| Descripción | Multimedia bridge/ high performance Scaler and PCI circuit SPCI | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7146A
Multimedia bridge, high
performance Scaler and PCI circuit
(SPCI)
Product specification
File under Integrated Circuits, IC22
1998 Apr 09
1 page  
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I/O
I2C-bus
Intel/
Motorola
I2S1-bus
I2S2-bus
Dual D1 or 16-bit YUV
SAA7146A
GPIO PORT
I2C-BUS MASTER
DEBI PORT
DEBI FIFO
AUDIO INPUT/OUTPUT
AUDIO INPUT/OUTPUT
TSL
AUDIO FIFO
RPS
TASK 1
TASK 2
EVENT
MANAGER
REAL TIME VIDEO INTERFACE
8-BIT D1 INPUT/OUTPUT
8-BIT D1 INPUT/OUTPUT
16-BIT YUV IN
YUV
HIGH PERFORMANCE SCALER
H-FILTER/SCALER
V-FILTER/SCALER
VIDEO-FLIP/MIRROR
COLOUR SPACE CV. GAMMA CORRECTION
PIXEL-FORMATTER/DITHER
YUV/RGB
VIDEO
FIFO1
CLIPPING
UNIT
VIDEO
FIFO2
YUV
BINARY
RATIO
SCALER
YUV
VIDEO
FIFO3
PCI INTERFACE
control
data
PCI BUS
MMU DMA AND INTERNAL ARBITRATION CONTROLLER
MHB044
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Product specification
SAA7146A
Pin description for SQFP208
SYMBOL
VSSD0
D1_A0
D1_A1
D1_A2
D1_A3
VDDD1
n.c.
VSSD1
D1_A4
D1_A5
D1_A6
D1_A7
VDDD2
n.c.
VSSD2
VS_A
HS_A
LLC_A
PXQ_A
n.c.
VDDD3
n.c.
VSSD3
TRST
TMS
TCLK
TDO
TDI
VDDD4
n.c.
VSSD4
INTA#
RST#
CLK
GNT#
REQ#
VDDD5
n.c.
PIN STATUS
DESCRIPTION
1 P digital ground 0
2 I/O bidirectional digital CCIR 656 D1 port A bit 0
3 I/O bidirectional digital CCIR 656 D1 port A bit 1
4 I/O bidirectional digital CCIR 656 D1 port A bit 2
5 I/O bidirectional digital CCIR 656 D1 port A bit 3
6 P digital supply voltage 1 (3.3 V)
7 − reserved pin; not connected internally
8 P digital ground 1
9 I/O bidirectional digital CCIR 656 D1 port A bit 4
10 I/O bidirectional digital CCIR 656 D1 port A bit 5
11 I/O bidirectional digital CCIR 656 D1 port A bit 6
12 I/O bidirectional digital CCIR 656 D1 port A bit 7
13 P digital supply voltage 2 (3.3 V)
14 − reserved pin; not connected internally
15 P digital ground 2
16 I/O bidirectional vertical sync signal port A
17 I/O bidirectional horizontal sync signal port A
18 I/O bidirectional line-locked system clock port A
19 I/O bidirectional pixel qualifier signal to mark valid pixels port A; note 1
20 − reserved pin; do not connect
21 P digital supply voltage 3 (3.3 V)
22 − reserved pin; not connected internally
23 P digital ground 3
24 I test reset input (JTAG pin must be set LOW for normal operation)
25 I test mode select input (JTAG pin must be floating or set to HIGH during normal
operation)
26 I test clock input (JTAG pin should be set LOW during normal operation)
27 O test data output (JTAG pin not active during normal operation)
28 I test data input (JTAG pin must be floating or set to HIGH during normal operation)
29 P digital supply voltage 4 (3.3 V)
30 − reserved pin; not connected internally
31 P digital ground 4
32 O PCI interrupt line output (active LOW)
33 I PCI global reset input (active LOW)
34 I PCI clock input
35 I bus grant input signal input, PCI arbitration signal (active LOW)
36 O bus request output signal output, PCI arbitration signal (active LOW)
37 P digital supply voltage 5 (3.3 V)
38 − reserved pin; not connected internally
1998 Apr 09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7146AHZ.PDF ] | |
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