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PDF SAA7118 Data sheet ( Hoja de datos )
| Número de pieza | SAA7118 | |
| Descripción | Multistandard video decoder with adaptive comb filter and component video input | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7118
Multistandard video decoder with
adaptive comb filter and component
video input
Preliminary specification
Supersedes data of 2000 Nov 27
File under Integrated Circuits, IC22
2001 May 30
1 page  
Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
It is a highly integrated circuit for desktop video and similar
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAA7118
accepts CVBS or S-video (Y/C) as analog inputs from TV
or VCR sources, including weak and distorted signals as
well as baseband component signals Y-PB-PR or RGB. An
expansion port (X-port) for digital video (bidirectional half
duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the SAA7118 supports 8 or 16-bit wide output data
with auxiliary reference data for interfacing to VGA
controllers.
The target application for the SAA7118 is to capture and
scale video images, to be provided as digital video stream
through the image port of a VGA controller, for capture to
system memory, or just to provide digital baseband video
to any picture improvement processing.
The SAA7118 also provides a means for capturing the
serially coded data in the vertical blanking interval
(VBI-data). Two principal functions are available:
1. To capture raw video samples, after interpolation to
the required output data rate, via the scaler
2. A versatile data slicer (data recovery) unit.
The SAA7118 also incorporates field-locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio during capture or playback.
All of the ADCs may be used to digitize a VSB signal for
subsequent decoding; a dedicated output port and a
selectable VSB clock input is provided.
The circuit is I2C-bus controlled (full write/read capability
for all programming registers, bit rate up to 400 kbits/s).
4 QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
UNIT
VDDD
VDDDC
VDDA
Tamb
PA+D
digital supply voltage
digital core supply voltage
analog supply voltage
ambient temperature
analog and digital power dissipation
note 1
3.0 3.3 3.6 V
3.0 3.3 3.6 V
3.1 3.3 3.5 V
0 − 70 °C
− 1.1 1.35 W
Note
1. Power dissipation is measured in component mode (four ADCs active) and 8-bit image port output mode, expansion
port is 3-stated.
5 ORDERING INFORMATION
TYPE
NUMBER
SAA7118E
SAA7118H
PACKAGE
NAME
DESCRIPTION
BGA156
QFP160
plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28 × 28 × 3.4 mm; high stand-off height
VERSION
SOT472-1
SOT322-2
2001 May 30
5
5 Page 
Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
PIN
SYMBOL
TYPE(1)
QFP160 BGA156
DESCRIPTION
XPD3
134 B9 I/O MSB − 4 of expansion port data
XPD2
135 A9 I/O MSB − 5 of expansion port data
VDDD11 136 M8
P digital supply voltage 11 (peripheral cells)
VSSD11 137 L8
P digital ground 11 (peripheral cells)
XPD1
138 B8 I/O MSB − 6 of expansion port data
XPD0
139 A8 I/O LSB of expansion port data
XRV
140 D8 I/O vertical reference I/O expansion port
XRH
141 C7 I/O horizontal reference I/O expansion port
VDDD12 142 M9
P digital supply voltage 12 (core)
XCLK
143 A7 I/O clock I/O expansion port
XDQ
144 B7 I/O data qualifier for expansion port
VSSD12 145 L9
P digital ground 12 (core)
XRDY
146 A6
O task flag or ready signal from scaler, controlled by XRQT
TRST
147 C6 I/pu test reset input (active LOW), for boundary scan test (with internal pull-up);
notes 2, 3 and 4
TCK
148 B6 I/pu test clock for boundary scan test; note 2
TMS
149 D6 I/pu test mode select input for boundary scan test or scan test; note 2
TDO
150 A5
O test data output for boundary scan test; note 2
VDDD13
TDI
151 M11
P digital supply voltage 13 (peripheral cells)
152 B5 I/pu test data input for boundary scan test; note 2
VSSD13
153 L11
VSS(xtal)
154
A4
XTALI
155 B4
P digital ground 13 (peripheral cells)
P ground for crystal oscillator
I input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or connection
of external oscillator with TTL compatible square wave clock signal
XTALO
156
A3
O 24.576 MHz (32.11 MHz) crystal oscillator output; not connected if TTL
clock input of XTALI is used
VDD(xtal)
157
B3
P supply voltage for crystal oscillator
XTOUT
158
A2
O crystal oscillator output signal; auxiliary signal
DNC9
159 C3 NC do not connect, reserved for future extensions and for testing
DNC10
160
C4
NC do not connect, reserved for future extensions and for testing
Notes
1. I = input, O = output, P = power, NC = not connected, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.
2. In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal
pull-up transistor and TDO is a 3-state output pad.
3. For board design without boundary scan implementation connect the TRST pin to ground.
4. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRST can be used to force the Test
Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
5. Pin strapping is done by connecting the pin to the supply via a 3.3 kΩ resistor. During the power-up reset sequence
the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping
resistor is necessary (internal pull-down).
2001 May 30
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet SAA7118.PDF ] | |
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