PDF SAA7104H Data sheet ( Hoja de datos )

Número de pieza	SAA7104H
Descripción	Digital video encoder
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA7104H; SAA7105H Digital video encoder Product speciﬁcation 2004 Mar 04 1 page This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VDDA1 VDDA2 VDDA3 VDDA4 VSSA1 VSSA2 VDDD1 VDDD2 VDDD3 VDDD4 VSSD1 VSSD2 VSSD3 VSSD4 43 44 52 53 48 49 6 12 25 58 7 13 26 57 PD11 to PD0 5 to 2, 64 to 61, 21 to 24 INPUT FORMATTER FIFO + UPSAMPLING LUT + CURSOR RGB TO Y-CB-CR MATRIX 20 PIXCLKI 19 PIXCLKI 36 LLC 38 SRES DECIMATOR 4 : 4 : 4 to 4:2:2 HORIZONTAL SCALER FIFO BORDER GENERATOR SAA7104H SAA7105H VERTICAL SCALER VERTICAL FILTER VIDEO ENCODER HD OUTPUT TRIPLE DAC PIXCLKO 27 PIXEL CLOCK SYNTHESIZER CRYSTAL OSCILLATOR TIMING GENERATOR I2C-BUS CONTROL 1, 16, 30 to 34 n.c. 37 RTCI 51 50 60 17 18 28 29 59 15 14 8 XTALI XTALO FSVGC CBO TTXRQ_XCLKO2 SDA SCL RESET 27 MHz VSVGC HSVGC TTX_SRES 55 TRST 47 DUMP 46 RSET 56 TDI 10 TDO 9 TMS 11 TCK 45 BLUE_CB_CVBS 42 GREEN_VBS_CVBS 41 RED_CR_C_CVBS 35 OUT_EN 39 VSM 40 HSM_CSYNC 54 TVD mhc683 Fig.1 Block diagram. 5 Page Philips Semiconductors Digital video encoder Product speciﬁcation SAA7104H; SAA7105H Table 2 Layout of a byte in the cursor bit map D7 D6 pixel n + 3 D1 D0 D5 D4 pixel n + 2 D1 D0 D3 D2 pixel n + 1 D1 D0 D1 D0 pixel n D1 D0 For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. The hot spot is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 3 Cursor bit map BYTE 0 1 2 ... 6 7 ... 254 255 D7 D6 D5 D4 D3 D2 D1 D0 row 0 row 0 row 0 row 0 column 3 column 2 column 1 column 0 row 0 row 0 row 0 row 0 column 7 column 6 column 5 column 4 row 0 column 11 row 0 column 10 row 0 row 0 column 9 column 8 ... ... ... ... row 0 column 27 row 0 column 26 row 0 column 25 row 0 column 24 row 0 column 31 row 0 column 30 row 0 column 29 row 0 column 28 ... ... ... ... row 31 column 27 row 31 column 26 row 31 column 25 row 31 column 24 row 31 column 31 row 31 column 30 row 31 column 29 row 31 column 28 Table 4 Cursor modes CURSOR PATTERN CURSOR MODE CMODE = 0 CMODE = 1 00 second cursor colour second cursor colour 01 ﬁrst cursor colour ﬁrst cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour 7.5 RGB Y-CB-CR matrix RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 7.6 Horizontal scaler The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. If the SAA7104H; SAA7105H input data is in accordance with “ITU-R BT.656”, the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output. 2004 Mar 04 11 11 Page

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