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PDF SAA6588T Data sheet ( Hoja de datos )
| Número de pieza | SAA6588T | |
| Descripción | RDS/RBDS pre-processor | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA6588
RDS/RBDS pre-processor
Product specification
File under Integrated Circuits, IC01
1997 Sep 01
1 page  
Philips Semiconductors
RDS/RBDS pre-processor
Product specification
SAA6588
PINNING
SYMBOL
MRO
MPTH
TCON
OSCO
OSCI
VSSD
VDDD
DAVN
SDA
SCL
PIN DESCRIPTION
1 multi-path rectifier output
2 multi-path detector output
3 test control input pin
4 oscillator output
5 oscillator input
6 digital ground (0 V)
7 digital supply voltage (5 V)
8 data available output (active LOW)
9 I2C-bus serial data I/O
10 I2C-bus serial clock input
SYMBOL
PSWN
MAD
AFIN
VDDA
VSSA
MPX
Vref
SCOUT
CIN
LVIN
PIN DESCRIPTION
11 pause switch output (active LOW)
12 slave address (LSB) input
13 audio signal input
14 analog supply voltage (5 V)
15 analog ground (0 V)
16 multiplex input signal
17 reference voltage output
18 band-pass filter output
19 comparator input
20 level input
handbook, halfpage
MRO 1
20 LVIN
MPTH 2
19 CIN
TCON 3
18 SCOUT
OSCO 4
OSCI 5
VSSD 6
VDDD 7
DAVN 8
17 Vref
16 MPX
SAA6588
15 VSSA
14 VDDA
13 AFIN
SDA 9
12 MAD
SCL 10
11 PSWN
MGK533
Fig.2 Pin configuration (DIP20).
handbook, halfpage
MRO 1
20 LVIN
MPTH 2
19 CIN
TCON 3
18 SCOUT
OSCO 4
17 Vref
OSCI 5
VSSD 6
16 MPX
SAA6588T
15 VSSA
VDDD 7
14 VDDA
DAVN 8
13 AFIN
SDA 9
12 MAD
SCL 10
11 PSWN
MGK534
Fig.3 Pin configuration (SO20).
1997 Sep 01
5
5 Page 
Philips Semiconductors
RDS/RBDS pre-processor
Product specification
SAA6588
I2C-BUS INTERFACE REGISTERS
The I2C-bus interface is connected to other blocks of the
pre-processor via internal registers (byte oriented). Those
can either be written by the pre-processor control and read
by the main controller I2C-bus or vice versa.
The device provides 3 input control registers to which may
be written via the I2C-bus and 7 output registers which
may be read via the I2C-bus.
The decoder control updates the output registers after the
detection of a new RDS/RBDS information block and
reads the new mode control settings of the input control
registers. Both operations may occur in the same time slot,
provided that the read operation is complete before a new
RDS/RBDS data bit is processed by the demodulator.
For the corresponding access the registers are addressed
by two separate register pointers, write-enable and
read-enable signals, which are activated either via the
decoder control or via the I2C-bus interface control.
During a read or write transmission from the I2C-bus the
read/write pointer selects the register of the first byte for
transmission and is auto-incremented by the I2C-bus
control for the transfer of subsequent bytes.
During a write transmission after reception of the device
slave address and write bit, the mode control settings for
the pre-processor have to be send in the protocol
sequence as shown in Table 1 and Fig.5.
During a read cycle after reception of the device slave
address and read bit the requested RDS/RBDS data has
to be received in the protocol sequence as given in Table 2
and Fig.7.
Table 1 Input control registers
DATA
Byte 0W
Byte 1W
Byte 2W
FUNCTION
initialization and mode control setting;
see Table 3
pause level and flywheel setting;
see Table 6
pause time/oscillator frequency and
quality detector sensitivity setting;
see Table 7
Table 2 Output registers
DATA
Byte 0R
Byte 1R
Byte 2R
Byte 3R
Byte 4R
Byte 5R
Byte 6R
FUNCTION
decoder and data status information;
see Table 12
last processed block (HIGH byte);
see Table 15
last processed block (LOW byte);
see Table 15
previously processed block (HIGH byte);
see Table 15
previously processed block (LOW byte);
see Table 15
error status information; see Table 15
signal quality indication; see Table 15
WRITE TRANSMISSION FORMAT
Table 3 Description of initialization and mode control
byte (byte 0W)
BIT NAME
FUNCTION
7 SQCM 0: triggered signal quality measurement
1: signal quality continuous measurement
6 TSQD 0: no determination of signal quality
1: trigger of signal quality detector
measurement
5 NWSY 0: normal processing mode
1: restart of synchronization
4 SYM1 selection of error correction mode for
3 SYM0 synchronization search; see Table 4
2 RBDS 0: RDS processing mode
1: RBDS processing mode
1 DAC1 selection of data output protocol and
0 DAC0 indirectly control of data available output
signal (DAVN); see Table 5
1997 Sep 01
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SAA6588T.PDF ] | |
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