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PDF SAA5355 Data sheet ( Hoja de datos )
| Número de pieza | SAA5355 | |
| Descripción | Single-chip colour CRT controller FTFROM | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA5355
Single-chip colour CRT controller
(FTFROM)
Product specification
File under Integrated Circuits, IC02
March 1986
1 page  
Philips Semiconductors
Single-chip colour CRT controller
(FTFROM)
Product specification
SAA5355
Fig.2 Pinning diagram.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage range (pin 40)
Maximum input voltage (except F6, TCS, REF)
Maximum input voltage (F6, TCS)
Maximum input voltage (REF)
Maximum output voltage
Maximum output current
Operating ambient temperature range
Storage temperature range
VDD
VImax
Vlmax
VREF
VOmax
IOmax
Tamb
Tstg
Outputs other than CLKO, OSCO, R, G, B, and VDS are short-circuit protected.
March 1986
5
−0,3 to + 7,5 V
−0,3 to + 7,5 V
−0,3 to + 10,0 V
−0,3 to + 3,0 V
−0,3 to + 7,5 V
10 mA
−20 to + 70 °C
−55 to + 125 °C
5 Page 
Philips Semiconductors
Single-chip colour CRT controller
(FTFROM)
Product specification
SAA5355
PARAMETER
SYMBOL MIN.
TYP.
MAX. UNIT
Microprocessor WRITE to FTFROM (Fig.10)
Write cycle time (note 11)
R/W LOW set-up to UDS fall
RE LOW to UDS fall
Address valid to UDS fall
UDS LOW time
Data valid to UDS rise
UDS LOW to DTACK LOW
UDS HIGH to DTACK rise
UDS HIGH to data hold
UDS HIGH to address hold
UDS HIGH to RE rise
UDS HIGH to R/W rise
F1/F6 to memory access cycle (Fig.11)
UDS HIGH to F6 (component of F1/F6) rise
F6 (component of F1/F6) HIGH to UDS rise
SYNCHRONIZATION and BLANKING
tWCY
tWUD
tRES
tASS
tLUS
tDSS
tDTA
tDTR
tDSH
tDSA
tSRE
tUDW
tUF6
tF6U
500 −
0−
30 −
30 −
100 −
80 −
0−
0−
10 −
10 −
10 −
0−
20 −
40 −
− ns
− ns
− ns
− ns
− ns
− ns
60 ns
75 ns
− ns
− ns
− ns
− ns
− ns
− ns
TCS, SAND, FS/DDA
See Fig.12 for timing relationships
and Fig.13 for vertical sync and
blanking waveforms.
Notes to the characteristics
1. Pin 30 must be biased externally.
2. Value under investigation
3. 16-level analogue voltage outputs.
4. Output voltage guaranteed when programmed for top level.
5. All timings are related to a 6,00 MHz clock.
6. CLKO, R, G, B, F1/F6, VDS: CL = 25 pF.
FS/DDA: CL = 50 pF
7. CLKO, F1/F6, VDS, FS/DDA: reference levels = 0,8 to 2,0 V
R, G, B: reference levels = 0,8 to 2,0 V with VREF = 2,7 V
8. These times may momentarily be reduced to a nominal 83 ns in slave-sync mode at the moment of
re-synchronization.
9. CL = 150 pF.
10. Reference levels = 0,8 to 2,0 V.
11. Microprocessor write cycle times of less than 500 ns are permitted but often result in Wait States being generated,
the precise timing of DTACK will then depend on the internal synchronization time.
March 1986
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA5355.PDF ] | |
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