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PDF SAA5250P Data sheet ( Hoja de datos )
| Número de pieza | SAA5250P | |
| Descripción | Interface for data acquisition and control for multi-standard teletext systems | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA5250
Interface for data acquisition and
control
(for multi-standard teletext
systems)
Product specification
File under Integrated Circuits, IC02
January 1987
1 page  
Philips Semiconductors
Interface for data acquisition and control
(for multi-standard teletext systems)
Product specification
SAA5250
PINNING FUNCTION
MNEMONIC
A10 and
A0 to A9
VAL OUT
VAL IN/SYNC
CBB
DCK
SD
MS
WE
DB7 to DB0
ALE
CE
WR
VSS
RD
D0 to D7
VDD
PIN NO. FUNCTION
1 and
30 to 39
2
3
4
Memory address outputs used by CIDAC to address a 2 K byte buffer memory
Validation output signal used to control the location of the window for the framing code.
Validation input signal (line signal) used to give or calculate a window for the framing
code detection
Colour burst blanking output signal used by the SAA5230 as a data slicer reset pulse
5 Data clock input, in synchronization with the serial data signal
6 Serial data input, arriving from the demodulator
7 Chip enable output signal for buffer memory selection
8 Write command output for the buffer memory
9 to 16
17
18
19
8-bit three state input/output data/address bus used to transfer commands, data and
status between the CIDAC registers and the CPU
Demultiplexing input signal for the CPU data bus
Chip enable input for the SAA5250
Write command input (when LOW)
20
21
22 to 29
40
ground
Read command input (when LOW)
8-bit three state input/output data bus used to transfer data between CIDAC and the
buffer memory
+5 V power supply
January 1987
5
5 Page 
Philips Semiconductors
Interface for data acquisition and control
(for multi-standard teletext systems)
Product specification
SAA5250
Fifo status register (read R0 register)
Table 11 Fifo register contents
DB2 TO DB0
DB2 = 1
memory empty
DB1 = 1, data not present in the
read data register
DB0 = 0
memory not full
Once the relevant prefix and the right working modes have been given by the corresponding registers, a write command
to the R6 register enables the CIDAC to accept and process serial data.
Channel comparator
This is a four bit comparator which compares the three user hexadecimal defined values in R1 and R2 to corresponding
bytes of the prefix coming from the Hamming corrector. If the three bytes match, the internal process of the prefix
continues. If they do not match the CIDAC returns to a wait state until the next broadcast data package is received.
FIFO memory controller
The FIFO memory contains all the necessary functions required for the control of the 11-bit address memory (2 K byte).
The functions contained in the FIFO memory are as follows:
• write address register (11-bits)
• read address register (11-bits)
• memory pointer (11-bits)
• address multiplexer (11-bits)
• write data register (8-bits)
• read data register (8-bits)
• data multiplexer
• control logic
The FIFO memory provides the memory interface with the following:
• 11-bit address bus (A10 to A0)
• 8-bit data bus (D7 to D0)
• two control signals, memory select (MS) and write enable (WE)
January 1987
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA5250P.PDF ] | |
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