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PDF SCANPSC110 Data sheet ( Hoja de datos )

Número de pieza SCANPSC110
Descripción SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! SCANPSC110 Hoja de datos, Descripción, Manual

October 1999
SCANPSC110F
SCAN Bridge Hierarchical and Multidrop Addressable
JTAG Port (IEEE1149.1 System Test Support)
General Description
The SCANPSC110F Bridge extends the IEEE Std. 1149.1
test bus into a multidrop test bus environment. The advan-
tage of a hierarchical approach over a single serial scan
chain is improved test throughput and the ability to remove a
board from the system and retain test access to the remain-
ing modules. Each SCANPSC110F Bridge supports up to 3
local scan rings which can be accessed individually or com-
bined serially. Addressing is accomplished by loading the in-
struction register with a value matching that of the Slot in-
puts. Backplane and inter-board testing can easily be
accomplished by parking the local TAP Controllers in one of
the stable TAP Controller states via a Park instruction. The
32-bit TCK counter enables built in self test operations to be
performed on one port while other scan chains are simulta-
neously tested.
n The 6 slot inputs support up to 59 unique addresses, a
Broadcast Address, and 4 Multi-cast Group Addresses
n 3 IEEE 1149.1-compatible configurable local scan ports
n Mode Register allows local TAPs to be bypassed,
selected for insertion into the scan chain individually, or
serially in groups of two or three
n 32-bit TCK counter
n 16-bit LFSR Signature Compactor
n Local TAPs can be tri-stated via the OE input to allow
an alternate test master to take control of the local TAPs
n The IP version of this device supports features not
described in this datasheet such as 8 slot inputs for
enhanced address capability and additional instructions.
For a completed description of the additional instructions
supported, refer to the SCANPSC110 supplemental
datasheet.
Features
n True IEEE1149.1 hierarchical and multidrop addressable
capability
Connection Diagrams
28-Pin
CDIP and Flatpak
Pin Assignment for LCC
DS100327-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100327
DS100327-2
www.national.com

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SCANPSC110 pdf
Overview of SCANPSC110F Bridge
Functions (Continued)
In multi-drop scan systems, a scan tester can select indi-
vidual ’PSC110Fs for participation in upcoming scan opera-
tions. ’PSC110F “selection” is accomplished by simulta-
neously scanning a device address out to multiple
’PSC110Fs. Through an on-chip address matching process,
only those ’PSC110Fs whose statically-assigned address
matches the scanned-out address become selected to re-
ceive further instructions from the scan tester. ’PSC110F se-
lection is done using a “Level-1” protocol, while follow-on in-
structions are sent to selected ’PSC110Fs by using a
“Level-2” protocol.
FIGURE 2. SCANPSC110F Bridge State Machines
DS100327-4
The ’PSC110F contains three distinct but coupled
state-machines (see Figure 2 ). The first of these is the
TAP-control state-machine, which is used to drive the
’PSC110Fs scan ports in conformance with the 1149.1 Stan-
dard (see Figure 17 of appendix). The second is the
’PSC110F-selection state-machine (Figure 3). The third
state-machine actually consists of three identical but inde-
pendent state-machines (see Figure 4), one per ’PSC110F
local scan port. Each of these scan port-selection
state-machines allows individual local ports to be inserted
into and removed from the ’PSC110Fs overall scan chain.
The ’PSC110F selection state-machine performs the ad-
dress matching which gives the ’PSC110F its multi-drop ca-
pability. That logic supports single-’PSC110F access,
multi-cast, and broadcast. The ’PSC110F-selection
state-machine implements the chip’s Level-1 protocol.
5 www.national.com

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SCANPSC110 arduino
Level 1 Protocol (Continued)
DS100327-8
FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register
DS100327-9
FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register
Level 2 Protocol
Once the SCANPSC110F Bridge has been successfully ad-
dressed and selected, its internal registers may be accessed
via Level-2 Protocol. Level-2 Protocol is compliant to IEEE
Std. 1149.1 TAP protocol with one exception: if the
’PSC110F is selected via the Broadcast or Multi-Cast ad-
dress, TDOB will always be TRI-STATED. (The TDOB buffer
must be implemented this way to prevent bus contention.)
Upon being selected, (i.e., the ’PSC110F Selection controller
transitions from the Wait-For-Address state to one of the Se-
lected states), each of the local scan ports (LSP1, LSP2,
LSP3) remains parked in one of the following four TAP Con-
troller states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, or
Pause-IR and the active scan chain will consist of: TDIB
through the instruction register (or the IDCODE register) and
out through TDOB.
TDIBInstruction RegisterTDOB
The UNPARK instruction (described later) is used to insert
one or more local scan ports into the active scan chain.
Table 4 describes which local ports are inserted into the
chain, and in what order.
LEVEL 2 INSTRUCTION TYPES
There are two types of instructions (reference Table 5):
11 www.national.com

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