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Número de pieza | SCAN92LV090 | |
Descripción | 9 Channel Bus LVDS Transceiver with 1149.1 Access | |
Fabricantes | National Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SCAN92LV090 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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SCAN92LV090
9 Channel Bus LVDS Transceiver w/ Boundary SCAN
General Description
The SCAN92LV090A is one in a series of Bus LVDS trans-
ceivers designed specifically for the high speed, low power
proprietary backplane or cable interfaces. The device oper-
ates from a single 3.3V power supply and includes nine
differential line drivers and nine receivers. To minimize bus
loading, the driver outputs and receiver inputs are internally
connected. The separate I/O of the logic side allows for loop
back support. The device also features a flow through pin out
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differ-
ential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with re-
duced EMI. In addition, the differential signaling provides
common mode noise rejection of ±1V.
The receiver threshold is less than ±100 mV over a ±1V
common mode range and translates the differential Bus
LVDS to standard (TTL/CMOS) levels.
This device is compliant with IEEE 1149.1 Standard Test
Access Port and Boundary Scan Architecture with the incor-
poration of the defined boundary-scan test logic and test
access port consisting of Test Data Input (TDI), Test Data
Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and
the optional Test Reset (TRST).
Features
n IEEE 1149.1 (JTAG) Compliant
n Bus LVDS Signaling
n Low power CMOS design
n High Signaling Rate Capability (above 100 Mbps)
n 0.1V to 2.3V Common Mode Range for VID = 200mV
n ±100 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 64 pin LQFP package and BGA
package
n High impedance Bus pins on power off (VCC = 0V)
Simplified Functional Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation DS101242
10124201
www.national.com
1 page DC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol
Parameter
Conditions
Pin Min Typ
VIH Minimum Input High
Voltage
VIL Maximum Input Low
Voltage
IIH Input High Current
IIL Input Low Current
VCL Input Diode Clamp
Voltage
VIN = VCC or 2.4V
VIN = GND or 0.4V
ICLAMP = −18 mA
DIN, DE,
RE, TCK,
TRST,
TMS, TDI
DIN, DE,
RE
2.0
GND
−20
−20
−1.5
±10
±10
−0.8
IIH Input High Current VIN = VCC
TDI, TMS,
TCK,
TRST
-20
IILR Input Low Current
VIN = GND, VCC = 3.6v
TDI, TMS,
TRST
-25
IIL
ICCD
ICCR
Input Low Current
Power Supply Current
Drivers Enabled,
Receivers Disabled
Power Supply Current
Drivers Disabled,
Receivers Enabled
VIN = GND
No Load, DE = RE = VCC,
DIN = VCC or GND
DE = RE = 0V, VID = ±300mV
TCK
VCC
-20
50
50
ICCZ
Power Supply Current,
Drivers and Receivers
TRI-STATE®
DE = 0V; RE = VCC,
DIN = VCC or GND
50
ICC
ICCS
Power Supply Current,
Drivers and Receivers
Enabled
Power Supply Current
(SCAN Test Mode),
Drivers and Receivers
Enabled
DE = VCC; RE = 0V,
DIN = VCC or GND,
RL = 27Ω
DE = VCC; RE = 0V,
DIN = VCC or GND,
RL = 27Ω, TAP in any state other
than Test-Logic-Reset
160
180
IOFF
COUTPUT
Power Off Leakage
Current
Capacitance @ Bus Pins
VCC = 0V or OPEN,
DIN, DE, RE = 0V or OPEN,
VAPPLIED = 3.6V (Port Pins)
DO+/RI+,
DO−/RI−
DO+/RI+,
DO−/RI−
−20
5
COUTPUT Capacitance @ ROUT
ROUT
7
Max
VCC
0.8
+20
+20
+20
-115
+20
80
80
80
210
230
+20
Units
V
V
µA
µA
V
µA
µA
µA
mA
mA
mA
mA
mA
µA
pF
pF
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol
Parameter
Conditions
Min Typ
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
tPHLD
tPLHD
tSKD1
tSKD2
tSKD3
tTLH
tTHL
Differential Prop. Delay High to Low (Note 8)
Differential Prop. Delay Low to High (Note 8)
Differential Skew |tPHLD–tPLHD| (Note 9)
Chip to Chip Skew (Note 12)
Channel to Channel Skew (Note 13)
Transition Time Low to High
Transition Time High to Low
RL = 27Ω,
Figure 2, Figure 3
CL = 10 pF
1.0 1.8
1.0 1.8
120
0.25
0.5
0.5
Max Units
2.6 ns
2.6 ns
ps
1.6 ns
0.55 ns
1.2 ns
1.2 ns
5 www.national.com
5 Page Description of Boundary-Scan
Circuitry
The SCAN92LV090 features two unique Scan test modes,
each which requires a unique BSDL model depending on the
level of test access and fault coverage goals. In the first
mode (Mode0), only the TTL Inputs and Outputs of each
transceiver are accessible via a 1149.1 compliant protocol.
In the second mode (Mode1), the TTL Inputs and Outputs
are accessible by a 1149.1 compliant method while the
Differential I/O pins are accessible by a 1149.1 compatible
technique which evaluates the signal integrity and modifies
the data in the differential BSR as appropriate.
All test modes are handled by the ATPG software, and BSDL
selection should be invisible to the user.
The BYPASS register is a single bit shift register stage
identical to scan cell TYPE1. It captures a fixed logic low.
Bypass Register Scan Chain Definition
Logic 0
10124209
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
Instruction Register Scan Chain Definition
10124210
MSB → LSB (Mode0)
Instruction Code
00000000
10000010
10000111
00000110
All Others
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
BYPASS
MSB → LSB (Mode1)
Instruction Code
10011001
10010010
10001111
00000110
All Others
Instruction
EXTEST
SAMPLE/PRELOAD
CLAMP
HIGHZ
BYPASS
10124220
Mode 0 Boundary Scan Register Configuration
10124221
Mode 1 Boundary Scan Register Configuration
11 www.national.com
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet SCAN92LV090.PDF ] |
Número de pieza | Descripción | Fabricantes |
SCAN92LV090 | 9 Channel Bus LVDS Transceiver with 1149.1 Access | National Semiconductor |
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