PDF SC68C562C1 Data sheet ( Hoja de datos )

Número de pieza	SC68C562C1
Descripción	CMOS dual universal serial communications controller CDUSCC
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS SC68C562 CMOS dual universal serial communications controller (CDUSCC) Product specification Supersedes data of 1994 Apr 27 IC19 Data Handbook 1998 Sep 04 Philips Semiconductors 1 page Philips Semiconductors CMOS Dual universal serial communications controller (CDUSCC) Product specification SC68C562 BLOCK DIAGRAM D0-D7 BUS BUFFER DTACKN RWN A1-A6 CSN RESETN RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN TxDAKAN/GPI2AN TxDAKBN/GPI2BN DTCN DONEN TRxCA/B RTxCA/B RTSBN/SYNOUTBN RTSAN/SYNOUTAN CTSA/BN DCDBN/SYNIBN DCDAN/SYNIAN A7 CONTROL LOGIC MPU INTERFACE DMA INTERFACE SPECIAL FUNCTION PINS INTERFACE/ OPERATION CONTROL ADDRESS DECODE R/W DECODE DMA CONTROL CCRA/B PCRA/B RSRA/B TRSRA/B ICTSRA/B GSR CMR1A/B CMR2A/B OMRA/B TRCR A/B FTLR A/B TRMR A/B CID CONTROL IRQN IACKN X1/CLK X2/IDCN INTERRRUPT CONTROL ICRA/B IERA/B IVR IVRM IER1 IER2 IER3 OSCILLATOR DUSCC LOGIC CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B DPLL A/B BRG COUNTER/ TIMER A/B C/T CLK MUX A/B CTCRA/B CTPRHA/B CTPRLA/B CTHA/B CTLA/B TRANSMIT A/B TRANS CLK MUX TPRA/B TTRA/B TX SHIFT REG TRANSMIT 16 DEEP FIFO TELRA/B CRC GEN SPEC CHAR GEN LOGIC RECEIVER A/B RCVR CLK MUX RPRA/B RTRA/B S1RA/B S2RA/B RCVR SHIFT REG RECEIVER 16 DEEP FIFO RFLRA/B CRC ACCUM BISYNC COMPARE LOGIC TxD A/B RxD A/B SD00253 1998 Sep 04 5 5 Page Philips Semiconductors CMOS Dual universal serial communications controller (CDUSCC) Product specification SC68C562 IRQN IACKN D0-D7 DTACHN12 tIALDDA tIALIAH tIALDDV INVALID tIAHDDI DATA VALID tDDVDAL tIALDAL tDALIAH Figure 4. Interrupt Cycle Timing tIAHDDF INVALID tIAHDAH tIAHDAZ SD00256 SYMBOL PARAMETER12 tIALIAH tIALDDA tIALDDV tIAHDDF tDDVDAL tIAHDAH tIAHDAZ tIALDAL tIAHDDI tDALIAH IACKN low to IACKN high IACKN low to data bus drivers active9 IACKN low to read data valid IACKN high to data bus floating Read data valid to DTACKN low9 IACKN high to DTACKN high IACKN high to DTACKN high impedance IACKN low to DTACKN low9 IACKN high to data bus invalid DTACKN low to IACKN high9 LIMITS INDUSTRIAL SC68C562 COMMERCIAL SC68C562 Min Max Min Max 140 130 5 10 140 130 60 60 20 20 80 70 110 100 30 ) 1 fCL 5 140 ) 1.5 fCL 40 ) 1 fCL 5 130 ) 1.5 fCL 00 UNIT ns ns ns ns ns ns ns ns ns ns IACKN IDCN tIALDCL SD00257 Figure 5. Interrupt Daisy Chain Timing SYMBOL PARAMETER tIALDCL IACKN low to IDCN (daisy chain) low LIMITS INDUSTRIAL SC68C562 COMMERCIAL SC68C562 Min Max Min Max 70 60 UNIT ns 1998 Sep 04 RWN CSN GPI1_N AND/OR GPI2_N tGIVCSL tCSLGII Figure 6. Input Port Timing 11 SD00258 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
SC68C562C1	CMOS dual universal serial communications controller CDUSCC	NXP Semiconductors
SC68C562C1A	CMOS dual universal serial communications controller CDUSCC	NXP Semiconductors
SC68C562C1N	CMOS dual universal serial communications controller CDUSCC	NXP Semiconductors

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