DataSheet.es    


PDF SC68C198A1A Data sheet ( Hoja de datos )

Número de pieza SC68C198A1A
Descripción Octal UART with TTL compatibility at 3.3V and 5V supply voltages
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



Hay una vista previa y un enlace de descarga de SC68C198A1A (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! SC68C198A1A Hoja de datos, Descripción, Manual

Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 338
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 339
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Functional Description . . . . . . . . . . . . . . . . . . . . . 340
Conceptual Overview . . . . . . . . . . . . . . . . . . . . . . . 340
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Asynchronous bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Synchronous bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Timing Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Sclk – System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Baud Rate Generator BRG . . . . . . . . . . . . . . . . . . . . . . . . 341
BRG Counters (Used for random baud rate generation) 341
Channel Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Detailed Descriptions . . . . . . . . . . . . . . . . . . . . . . . 342
Receiver and Transmitter . . . . . . . . . . . . . . . . . . . 342
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Transmitter Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Transmission of ”break” . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
1x and 16x modes, Transmitter . . . . . . . . . . . . . . . . . . . . . 343
Transmitter FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
1x and 16x mode, Receiver . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
RxFIFO Status: Status reporting modes . . . . . . . . . . . . . . 344
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Character Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Xon Xoff Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Multi-drop or Wake up or 9 bit mode . . . . . . . . . . . . . . . . . 345
Character Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Interrupt Arbitration and IRQN generation . . . . . . . . . . . . . . . . 345
IACKN Cycle, Update CIR . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Enabling and Activating Interrupt sources . . . . . . . . . . . . . 346
Setting Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . 347
Major Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Minor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Watch-dog Timer Time–out Mode . . . . . . . . . . . . . . . . . . . 348
Wake Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Xon/Xoff Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
REGISTER DEfiniTIONS . . . . . . . . . . . . . . . . . . . . 351
MR – Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
UCIR – Update CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
General Purpose Output Pin Control . . . . . . . . 361
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Register Map Summary . . . . . . . . . . . . . . . . . . . . . 363
Register Map Detail . . . . . . . . . . . . . . . . . . . . . . . . 364
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Device Configuration after Hardware Reset or CRa cmd=x1F 372
Cleared registers: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Clears Modes for: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Disables: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Halts: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Limitations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
DC Electrical Specifications
(26C198 and 68C198) . . . . . . . . . . . . . . . . . . . . . . . 373
DC Electrical Specifications
(26L198 and 68L198) . . . . . . . . . . . . . . . . . . . . . . . 376
AC Electrical Characteristics5 (26L198 and
68L198) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
DESCRIPTION
The Philips 26C198 Octal UART is a single chip CMOS–LSI
communications device that provides 8 full-duplex asynchronous
channels with significantly deeper 16 byte FIFOs, Automatic
in–band flow control using Xon/Xoff characters defined by the user
and address recognition in the wake up mode. Synchronous bus
interface is used for all communication between host and OCTART.
It is fabricated using Philips 1.0 micron CMOS technology that
combines the benefits of low cost, high density and low power
consumption.
The operating speed of each receiver and transmitter can be
selected independently from one of 22 fixed baud rates, a 16X clock
derived from one of two programmable baud rate counters or one of
three external 16X clocks (1 available at 1x clock rate). The baud
rate generator and counter can operate directly from a crystal or
from seven other external or internal clock inputs. The ability to
independently program the operating speed of the receiver and
transmitter makes the Octal UART particularly attractive for dual
speed full duplex channel applications such as clustered terminal
systems. The receivers and transmitters are buffered with FIFOs of
16 characters to minimize the potential for receiver overrun and to
reduce interrupt overhead. In addition, a handshaking capability and
in–band flow control are provided to disable a remote UART
transmitter when the receiver buffer is full or nearly so.
To minimize interrupt overhead an interrupt arbitration system is
included which reports the context of the interrupting UART via
direct access or through the modification of the interrupt vector. The
context of the interrupt is reported as channel number, type of
device interrupting ( receiver COS etc.) and, for transmitters or
receivers, the fill level of the FIFO.
The Octal UART provides a power down mode in which the
oscillator is stopped but the register contents are maintained. This
results in reduced power consumption of several orders of
magnitudes. The Octal UART is fully TTL compatible when
operating from a single +5V power supply. Operation at 3.3 volts is
maintained with CMOS interface levels.
The device also offered in a version which maintains TTL input and
output levels while operating with a 3.3 volt power supply.
1995 May 1
336 853-1756 15179

1 page




SC68C198A1A pdf
Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
BLOCK DIAGRAM
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
INPUT BUFFERS AND OUTPUT DRIVERS
Block Diagram SC26/68C198
SD00193
As shown in the block diagram, the Octal UART consists of: an
interrupt arbiter, host interface, timing blocks and eight UART
channel blocks. The eight channels blocks operate independently,
interacting only with the timing, host I/F and interrupt blocks.
cycles after CEN is recognized. These four cycles are the C1, C2,
C3, C4 periods shown in the timing diagrams. DACKN always
occurs in the C4 time and occurs approximately 18 ns after the
rising edge of C4.
FUNCTIONAL DESCRIPTION
The SC26C198 is composed of several functional blocks:
Synchronous host interface block
A timing block consisting of a common baud rate generator
making 22 industry standard baud rates and 2 16–bit counters
used for non–standard baud rate generation
4 identical independent full duplex UART channel blocks
Interrupt arbitration system evaluating 24 contenders
I/O port control section and change of state detectors.
Addressing of the various functions of the OCTART is through the
address bus A(7:0). The 26C198 is compatible with the SC28L194
Quad UART in software and function. A[7], in a general sense, is
used to separate the data portion of the circuit from the control
portion.
Asynchronous bus cycle
The asynchronous mode requires one bus cycle of the chip select
(CEN) for each read or write to the chip. No more action will occur
on the bus after the C4 time until CEN is returned high.
Synchronous bus cycle
In the synchronous mode a read or write will be done every four
cycles of the Sclk. CEN does not require cycling but must remain
low to keep the synchronous accesses active. This provides a burst
mode of access to the chip.
CONCEPTUAL OVERVIEW
Host Interface
The Host interface is comprised of the signal pins CEN, W/RN,
IACKN, DACKN, IRQN Sclk and provides all the control for data
transfer between the external and internal data buses of the host
and the OCTART. The host interface operates in a synchronous
mode with the system (Sclk) which has been designed for a nominal
operating frequency of 33 MHz. The interface operates in either of
two modes; synchronous or asynchronous to the Sclk However
the bus cycle within the OCTART always takes place in four Sclk
In both cases each read or write operation(s) will be completed in
four (4) Sclk cycles. The difference in the two modes is only that the
asynchronous mode will not begin another bus cycle if the CEN
remains active after the four internal Sclk have completed. Internally
the asynchronous cycle will terminate after the four periods of Sclk
regardless of how long CEN is held active
In all cases the internal action will terminate at the withdrawal of
CEN. Synchronous CEN cycles shorter than multiples of four Sclk
cycles minus 1 Sclk and asynchronous CEN cycles shorter than four
Sclk cycles may cause short read or write cycles and produce
corrupted data transfers.
1995 May 1
340

5 Page





SC68C198A1A arduino
Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
every 22 Sclk cycles. New arbitration values presented to the
arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The priority of the
receivers and transmitters is controlled by the fill level of their
respective FIFOs. The more filled spaces in the RxFIFO the higher
the bid value; the more empty spaces in the TxFIFO the higher its
priority. Channels whose programmable high order bits are set will
be given interrupt priority higher than those with zeros in their high
order bits , thus allowing increased flexibility. The transmitter and
receiver bid values contain the character counts of the associated
FIFOs as high order bits in the bid value. Thus, as a receiver’s
RxFIFO fills, it bids with a progressively higher priority for interrupt
service. Similarly, as empty space in a transmitter’s TxFIFO
increases, its interrupt arbitration priority increases.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the OCTART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ”Update CIR” command) was asserted.
The Octal UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or ,when ”Interrupt Vector Modification is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ”Update CIR” command is given to the OCTART. The
interrupting channel and interrupt type fields of the CIR set the
current ”interrupt context” of the OCTART. The channel component
of the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel b receiver. At another
time read of the GRxFIFO may read the channel D RxFIFO (CIR
holds a channel D receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting and interrupt. In this
condition there is no arbitration value that exceeds the threshold
value.
Polling
Many users prefer polled to interrupt driven service where there are
a large number of fast data channels and/or the host CPU’s other
interrupt overhead is low. The Octal UART is functional in this
environment.
The most efficient method of polling is the use of the ”update CIR”
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
contains 0s, no interrupt is awaiting service. If the value is
non–zero, the fields of the CIR may be decoded for type, channel
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected arbitration value that
exceeds the threshold value.
Traditional methods of polling status registers may also be used.
They of course are less efficient but give the most variable and
quickest method of changing the order in which interrupt sources
are evaluated and interrogated.
Enabling and Activating Interrupt sources
An interrupt source becomes enabled when its interrupt capability is
set by writing to the Interrupt Mask Register, IMR. An interrupt
source can never generate an IRQN or have its ”bid” or interrupt
number appear in the CIR unless the source has been enabled by
the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ”bidding”
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting Interrupt Priorities
The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in the table below: The value
represented by the bits 9 to 3 in the table below are compared
against the value represented by the “Threshold. The “Threshold”
,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such
that bit 6 of the threshold is compared to bit 9 of the interrupt value
generated by any of the sources. When ever the value of the
interrupt source is greater than the threshold the interrupt will be
generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel D having the highest arbitration number. The decreasing
order is H to A. If all other parts of an arbitration are equal then the
channel number will determine which channel will dominate in the
arbitration process
.
1995 May 1
346

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet SC68C198A1A.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
SC68C198A1AOctal UART with TTL compatibility at 3.3V and 5V supply voltagesNXP Semiconductors
NXP Semiconductors

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar