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PDF sc3018b Data sheet ( Hoja de datos )
| Número de pieza | sc3018b | |
| Descripción | Quartz SAW Frequency Stability | |
| Fabricantes | RF Monolithics Inc | |
| Logotipo |  |
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• Quartz SAW Frequency Stability
• Fundamental Fixed Frequency
• Very Low Jitter and Power Consumption
• Rugged, Miniature, Surface-Mount Case
• Low-Voltage Power Supply (3.3 VDC)
This digital clock is designed for use with high-speed CPUs and communication equipment. Fundamental-
mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jit-
ter, compact size, and low power consumption. Differential outputs provide a sine wave that is capable of
driving 50 Ω loads.
SC3018B
250.0 MHz
Differential
Sine-Wave
Clock
Rating
Power Supply Voltage (VCC at Terminal 1)
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
Electrical Characteristics
Output Frequency
Q and Q Output
Q and Q Period Jitter
Output (Disabled)
Characteristic
Absolute Frequency
Tolerance from 250.00 MHz
Voltage into 50Ω (VSWR ≤ 1.2)
Operating Load VSWR
Symmetry
Harmonic Spurious
Nonharmonic Spurious
No Noise on VCC
200 mVP-P from 1 MHz to ½ fO on
Amplitude into 50 Ω
Output DC Resistance (between Q & Q)
ENABLE (Terminal 14)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
DC Power Supply
Operating Voltage
Operating Current
Operating Ambient Temperature
Lid Symbolization (YY = Year, WW = Week)
Value
0 to +4.0
0 to +4.0
-40 to +85
Units
VDC
VDC
°C
SMC-8 Case
Sym
fO
∆fO
VO
VIH
VIL
IIH
IIL
tPD
VCC
ICC
TA
Notes
1, 2
Minimum
249.950
Typical
Maximum
250.050
±200
0.60
1, 3
1.1
2:1
3, 4, 5
49
51
3, 4, 6
-30
-60
3, 4, 6, 7
15 30
3, 4, 7, 8
35
3, 9 75
3 50
VCC-0.1
0.0
VCC
VCC+0.1
0.20
3, 9 3 5
-1
1
+3.13
+3.30
+3.47
1, 3
20 40
1, 3 0
+70
RFM SC3018B 250.00 MHz YYWW
Units
MHz
ppm
VP-P
%
dBc
dBc
psP-P
psP-P
mVP-P
KΩ
V
V
mA
mA
ms
VDC
mA
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1. Unless otherwise noted, all specifications include any combination of load 6. Jitter and other spurious outputs induced by externally generated electrical noise
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to
ground. (See: Typical Test Circuit.)
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
2. One or more of the following United States patents apply: 4,616,197; 4,670,681; 7. Applies to period jitter of Q and Q. Measurements are made with the Tektronix
4,760,352.
CSA803 signal analyzer with at least 1000 samples.
3. The design, manufacturing process, and specifications of this device are subject 8. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
4.
5.
to change without notice.
Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and
nominal power supply voltage.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
9.
of fO at the VCC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
RF Monolithics, Inc. Phone: (972) 233-2903
Fax: (972) 387-9148
RFM Europe
Phone: 44 1963 251383
Fax: 44 1963 251510
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
E-mail: [email protected]
http://www.rfm.com
SC3018B-111799
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