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Número de pieza SC28L194A1A
Descripción Quad UART for 3.3V and 5V supply voltage
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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INTEGRATED CIRCUITS
SC28L194
Quad UART for 3.3V and 5V supply
voltage
Preliminary specification
Supersedes data of 1995 Dec 14
IC19 Data Handbook
1998 Sep 21
Philips
Semiconductors

1 page




SC28L194A1A pdf
Philips Semiconductors
Quad UART for 3.3V and 5V supply voltage
Preliminary specification
SC28L194
BLOCK DIAGRAM
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
FULL DUPLEX UART CHANNEL
INPUT BUFFERS AND OUTPUT DRIVERS
Block Diagram SC28L194
Figure 2. Block Diagram
SD00524
As shown in the block diagram, the Quad UART consists of an
interrupt arbiter, host interface, timing blocks and four UART channel
blocks. The four channels blocks operate independently, interacting
only with the timing, host I/F and interrupt blocks.
FUNCTIONAL DESCRIPTION
The SC28L194 is composed of several functional blocks:
Synchronous host interface block
A timing block consisting of a common baud rate generator
making 22 industry standard baud rates and 2 16-bit counters
used for non-standard baud rate generation
4 identical independent full duplex UART channel blocks
Interrupt arbitration system evaluating 24 contenders
I/O port control section and change of state detectors.
CONCEPTUAL OVERVIEW
Host Interface
The Host interface is comprised of the signal pins CEN, W/RN,
IACKN, DACKN, IRQN Sclk and provides all the control for data
transfer between the external and internal data buses of the host
and the QUART. The host interface operates in a synchronous mode
with the system (Sclk) which has been designed for a nominal
operating frequency of 33 MHz. The interface operates in either of
two modes; synchronous or asynchronous to the Sclk However
the bus cycle within the QUART always takes place in four Sclk
cycles after CEN is recognized. These four cycles are the C1, C2,
C3, C4 periods shown in the timing diagrams. DACKN always
occurs in the C4 time and occurs approximately 18 ns after the
rising edge of C4.
Addressing of the various functions of the QUART is through the
address bus A(7:0). To maintain upward compatibility with the
SC28L/C198 Octart the 8 bit address is still defined as such.
However A(6) is NOT used and is internally connected to Vss
(ground). The pin is, therefore, not included in the pin diagram. The
address space is controlled by A(5:0) and A(7). A[7], in a general
sense, is used to separate the data portion of the circuit from the
control portion.
Asynchronous bus cycle
The asynchronous mode requires one bus cycle of the chip select
(CEN) for each read or write to the chip. No more action will occur
on the bus after the C4 time until CEN is returned high.
Synchronous bus cycle
In the synchronous mode a read or write will be done every four
cycles of the Sclk. CEN does not require cycling but must remain
low to keep the synchronous accesses active. This provides a burst
mode of access to the chip.
In both cases each read or write operation(s) will be completed in
four (4) Sclk cycles. The difference in the two modes is only that the
asynchronous mode will not begin another bus cycle if the CEN
remains active after the four internal Sclk have completed. Internally
the asynchronous cycle will terminate after the four periods of Sclk
regardless of how long CEN is held active
In all cases the internal action will terminate at the withdrawal of
CEN. Synchronous CEN cycles shorter than multiples of four Sclk
cycles minus 1 Sclk and asynchronous CEN cycles shorter than four
Sclk cycles may cause short read or write cycles and produce
corrupted data transfers.
Timing Circuits
The timing block consists of a crystal oscillator, a fixed baud rate
generator (BRG), a pair of programmable 16 bit register based
counters. A buffer for the System Clock generates internal timing for
processes not directly concerned with serial data flow.
Crystal Oscillator
The crystal oscillator operates directly from a crystal, tuned between
1.0 and 8.0 MHz, connected across the X1/CCLK and X2 inputs with
a minimum of external components. BRG values listed for the clock
select registers correspond to a 3.6864 MHz crystal frequency. Use
of a 7.3728 MHz crystal will double the Communication Clock
frequencies.
An external clock in the 100 KHz to 10 MHz frequency range may
be connected to X1/CCLK. If an external clock is used instead of a
crystal, X1/CCLK must be driven and X2 left floating. The X1 clock
serves as the basic timing reference for the baud rate generator
(BRG) and is available to the BRG timers. The X1 oscillator input
1998 Sep 21
5

5 Page





SC28L194A1A arduino
Philips Semiconductors
Quad UART for 3.3V and 5V supply voltage
Preliminary specification
SC28L194
be given interrupt priority higher than those with zeros in their high
order bits , thus allowing increased flexibility. The transmitter and
receiver bid values contain the character counts of the associated
FIFOs as high order bits in the bid value. Thus, as a receiver’s
RxFIFO fills, it bids with a progressively higher priority for interrupt
service. Similarly, as empty space in a transmitter’s TxFIFO
increases, its interrupt arbitration priority increases.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the QUART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the “Update CIR” command) was asserted.
The Quad UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or ,when “Interrupt Vector Modification is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an “Update CIR” command is given to the QUART. The
interrupting channel and interrupt type fields of the CIR set the
current “interrupt context” of the QUART. The channel component of
the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel b receiver. At another
time read of the GRxFIFO may read the channel D RxFIFO (CIR
holds a channel D receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting an interrupt. In this condition
there is no arbitration value that exceeds the threshold value.
Polling
Many users prefer polled to interrupt driven service where there are
a large number of fast data channels and/or the host CPU’s other
interrupt overhead is low. The Quad UART is functional in this
environment.
The most efficient method of polling is the use of the “update CIR”
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
contains 0s, no interrupt is awaiting service. If the value is non-zero,
the fields of the CIR may be decoded for type, channel and
character count information. Optionally, the global interrupt registers
may be read for particular information about the interrupt status or
use of the global RxD and TxD registers for data transfer as
appropriate. The interrupt context will remain in the CIR until another
update CIR command or an IACKN cycle is initiated by the host
CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected arbitration value that
exceeds the threshold value.
Traditional methods of polling status registers may also be used.
They of course are less efficient but give the most variable and
quickest method of changing the order in which interrupt sources
are evaluated and interrogated.
Enabling and Activating Interrupt Sources
An interrupt source becomes enabled when its interrupt capability is
set by writing to the Interrupt Mask Register, IMR. An interrupt
source can never generate an IRQN or have its “bid” or interrupt
number appear in the CIR unless the source has been enabled by
the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt “bidding”
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting Interrupt Priorities
The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in the table below: The value
represented by the bits 9 to 3 in the table below are compared
against the value represented by the “Threshold. The “Threshold”
,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such
that bit 6 of the threshold is compared to bit 9 of the interrupt value
generated by any of the sources. When ever the value of the
interrupt source is greater than the threshold the interrupt will be
generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel D having the highest arbitration number. The decreasing
order is D-to-A. If all other parts of an arbitration are equal then the
channel number will determine which channel will dominate in the
arbitration process.
1998 Sep 21
11

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