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Número de pieza SC28C94A1N
Descripción Quad universal asynchronous receiver/transmitter QUART
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
SC28C94
Quad universal asynchronous
receiver/transmitter (QUART)
Product specification
1998 Aug 19
Replaces SC26C94 of 1995 May 01 and SC68C94 of 1995 May 01
IC17 Data Handbook
Philips
Semiconductors

1 page




SC28C94A1N pdf
Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC28C94
PIN DESCRIPTION
MNEMONIC TYPE
NAME AND FUNCTION
CEN
I Chip Select: Active low input that, in conjunction with RDN or WRN, indicates that the host MPU is trying to
access a QUART register. CEN must be inactive when IACKN is asserted.
A5:0
I Address Lines: These inputs select a 28C94 register to be read or written by the host MPU.
D7:0
I/O 8-bit Bidirectional Data Bus: Used by the host MPU to read and write 28C94 registers.
RDN
I Read Strobe: Active low input. When this line is asserted simultaneously with CEN, the 28C94 places the
contents of the register selected by A5:0 on the D7:0 lines.
WRN
I Write Strobe: Active low input. When this line is asserted simultaneously with CEN, the 28C94 writes the data
on D7:0 into the register selected by A5:0.
DACKN
O Data ACKnowledge: Active low, open-drain output to the host MPU, which is asserted subsequent to a read or
write operation. For a read operation, assertion of DACKN indicates that register data is valid on D7:0. For a
write operation, it indicates that the data on D7:0 has been captured into the indicated register. This signal
corresponds to READYN on 80x86 processors and DTACKN on 680x0 processors.
IRQN
O Interrupt Request: This active low open-drain output to the host MPU indicating that one or more of the
enabled UART interrupt sources has reached an interrupt value which exceeds that pre-programmed by host
software. The IRQN can be used directly as a 680x0 processor input; it must be inverted for use as an 80x86
interrupt input. This signal requires an external pull-up resistor.
IACKN
I Interrupt ACKnowledge: Active low input indicates host MPU is acknowledging an interrupt requested. The
28C94 responds by placing an interrupt vector or interrupt vector modified on D7-D0 and asserting DACKN. This
signal updates the CIR register in the interrupt logic. CEN must be high during this cycle.
TDa-d
O Transmit Data: Serial outputs from the four UARTs.
RDa-d
I Receive Data: Serial inputs to the four UARTs/
I/O0a-d
I/O Input/Output 0: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, Clear to Send inputs, 1X or 16X Transmit Clock outputs or general purpose outputs. Change-of-state
detection is provided for these pins. I/O pins have approximately 1.5 Mohm pull–up device.
I/O1a-d
I/O Input/Output 1: A multi-use input or output signal for each UART. These pins can be used as general purpose
or 1X or 16X transmit clock inputs, or general purpose 1X or 16X receive clock outputs. Change-of-state
detection is provided for these pins. In addition, I/O1a and I/O1c can be used as Counter/Timer inputs and I/O1b
and I/O1d can be used as Counter/Timer outputs. I/O pins have approximately 1.5 Mohm pull–up device.
I/O2a-d
I/O Input/Output 2: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, 1X or 16X receive clock inputs, general purpose outputs, RTS output or 1X or 16X receive clock outputs.
I/O pins have approximately 1.5 Mohm pull–up device.
I/O3a-d
I/O Input/Output 3: A multi-use input or output signal for each UART. These pins can be used as general purpose
inputs, 1X or 16X transmit clock inputs, general purpose outputs, or 1X or 16X transmit clock outputs. I/O pins
have approximately 1.5 Mohm pull–up device.
RESET
I Master Reset: Active high reset for the 28C94 logic. Must be asserted at power-up, may be asserted at other
times that the system is to be reset and restarted. OSC set to divide by 1, MR pointer set to 1, DACKN enabled,
I/O pins to input. Registers reset: MR0, OPR, CIR. IRQN, DTACKN, IVR Interrupt Vector, Power Down, Test
registers, FIFO pointers, Baud rate generator, Error Status, Watch Dog Timers, Change of State detectors,
counter/timer to timer, Transmitter and Receiver controllers and all interrupt bits. If reset pin is not used, then
first chip access should be to celar ‘power-down’ mode.
X1/CLK
I Crystal 1 or Communication Clock: This pin is normally connected to one side of a 3.6864MHz or a
7.3728MHz crystal, or can be connected to an external clock up to 8MHz.
X2 O Crystal 2: If a crystal is used, this pin should be connected to its other terminal. If an external clock is applied to
X1, this pin should be left unconnected.
VCC, VSS
Power and grounds: respectively.
A0-A5
D (7:0)
DTACKN
IACKN
BUS
INTERFACE
BLOCK A
COUNTER/TIMER
I/O PORT CONTROL
UARTS A/B
BAUD
RATE
GENERATOR
INTERRUPT CONTROL
BLOCK B
UARTS C/D
I/O CONTROL
I/O PORT CONTROL
Figure 4. Channel Architecture
SD00161
1998 Aug 19
5

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SC28C94A1N arduino
Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC28C94
The interrupt arbitration logic insures that the interrupt with the
numerically largest bid value will be the only source driving the
interrupt bus at the end of the arbitration period. The arbitration
period follows the period of the X1 clock. The maximum speed is
4.0MHz. If a higher speed X1 clock is used then the X1 clock “divide
by 2” feature must be used.
The value of the winning bid determined during the arbitration cycle
is compared to the “Interrupt Threshold” contained in the ICR
(Interrupt Control Register). If the winning bid exceeds the value of
the ICR the IRQN is asserted.
Priority Arbitration and Bidding
Each of the five “types” of interrupts has slightly different “bid” value,
as follows:
Receivers
# rcv’d
rEr
11
Chan #
3
1 11
2
Transmitters
0 # avail
10
Chan #
13
11
2
Break Detect
Programmable
10 0
Chan #
3
11
1
2
Change of State
Programmable
3
Counter/Timer
Programmable
2
00 1
11
1
0 10 1
1 11 1
Chan #
2
Chan #
2
SD00162
Please see “Interrupt Notes” at the end of this specification.
Bits shown above as ‘0’ or ‘1’ are hard-wired inputs to the arbitration
logic. Their presence allows determination of the interrupt type and
they insure that no bid will have a value of all zeros (a condition that
is indistinguishable from not bidding at all). They also serve to set a
default priority among the non-receive/transmit types when the
programmable fields are all zeros.
The channel number always occupies the two LSBs. Inclusion of
the channel number insures that a bid value generated will be
unique and that a single “winner” will drive the Interrupt Bus at the
end of the arbitration interval. The channel number portion of each
UARTs bid is hard-wired with UARTa being channel number 0 and
so forth.
As can be seen above, bits 4:2 of the winning bid value can be used
to identify the type of interrupt, including whether data was received
correctly or not. Like the Channel number field, these bits are
hard-wired for each interrupt source.
The “# rcv’d” and “# avail” fields indicate the number of bytes
present in the receiver FIFO and the number of empty bytes in the
transmitter FIFO, respectively.
NOTE: When there are zero bytes in the receiver’s FIFO, it does
NOT bid. Similarly, a full transmitter FIFO makes NO bid. In the
case where all bids have been disabled by the Interrupt Mask
Register or as a result of their byte counts, the active-low Interrupt
Bus will return FFh. This value always indicates no interrupt source
is active and IRQN will be negated.
The high order bit of the transmitter “bid” is always zero. An empty
transmit FIFO is, therefore, fixed at a lower interrupt priority than a
1/2 full receive FIFO. Bit 4 of a receiver bid is the Receiver Error Bit
(RER). The RER is the OR of the parity, framing and overrun error
conditions. The RER does little to modify the priority of receiver
interrupts vs. transmitter interrupts. It is output to the Interrupt Bus
to allow inclusion of good data vs. problem data information in the
Current Interrupt Register.
The high order bits of bids for received break, CoS (Change of
State) and Counter/Timer events are all programmable. By
programming ones in these fields, the associated interrupt source
can be made more significant than most receiver and all transmitter
interrupts. Values near zero in these fields makes them lower
priority classes of interrupt.
The channel address for C/T ab will be encoded as channel B (01)
The channel address for C/T cd will be encoded as channel D (11)
As shown in Figure 8, the bid arbitration process is controlled by the
EVAL/HOLDN signal derived from the oscillator clock.
Receipt of an IACKN signal from the host MPU latches the latest
“winning bid” from the latched Interrupt Bus into the Current Interrupt
Register (CIR). This logic is diagrammed in Figure 9.
If the IACKN falling edge of Figure 8 occurs during EVAL time, the
result from the last arbitration (captured by the Interrupt Bus latches)
is stored in CIR. Otherwise, the next EVAL pulse is inhibited and the
value in the Interrupt Bus Latches is stored in CIR.
Clearing the Interrupt
Activities which change the state of the ISR will cause the IRQN to
assert or negate. In addition, the accessing of a global or local
RxFIFO or TxFIFO reduces the associated byte count for transmitter
and receiver data interrupts. If the byte count falls below the
threshold value, the interrupt request is withdrawn. Other interrupt
conditions are cleared when the interrupting source is cleared.
Once the interrupt is cleared, the programmable value lowered or its
byte count value reduced by one of the methods listed above, a
different bidder (or no bidder at all) will win the on-going arbitration.
When the winning bid drops below the Interrupt Threshold
Register’s value, the IRQN pin will negate.
Arbitration - Aftermath
At the end of the arbitration, i.e., the falling edge of EVAL, the
winning interrupt source is driving its Channel number, number of
bytes (if applicable) and interrupt type onto the Interrupt Bus. These
values are captured into a latch by the trailing edge of EVAL. The
output of this latch is used by the Interrupt Threshold comparator;
the winning value is captured into another set of latches called the
Current Interrupt Register (CIR) at the time of an Interrupt
Acknowledge cycle or execution of the “Update CIR” command.
The Current Interrupt Register and associated read logic is shown in
Figure 9. Interrupting channel number and the three bit interrupt
type code and FIFO fill level are readable via the Internal Data Bus.
The contents of the appropriate receiver or transmitter byte
“counter”, as captured at the time of IACKN assertion, make up bits
7:5 of the CIR. If the interrupt type stored in the Current Interrupt
Register is not a receiver or transmitter data transfer type, the
CIR7:5 field will read as the programmable fields of their respective
bid formats.
The buffers driving the CIR to the DBUS also provide the means of
implementing the Global Interrupting Channel and Global Byte
Count Registers, described in a later section.
The winning bid channel number and interrupt type fields can also
be used to generate part of the Interrupt Vector, as defined by the
Interrupt Control Register.
1998 Aug 19
11

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