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Número de pieza SC26C94C1N
Descripción Quad universal asynchronous receiver/transmitter QUART
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
Product specification
Quad universal asynchronous receiver/transmitter (QUART) SC26C94
DESCRIPTION
The 26C94 quad universal asynchronous receiver/transmitter
(QUART) combines four enhanced Philips Semiconductors
industry-standard UARTs with an innovative interrupt scheme that
can vastly minimize host processor overhead. It is implemented
using Philips Semiconductors’ high-speed CMOS process that
combines small die size and cost with low power consumption.
The operating speed of each receiver and transmitter can be
selected independently at one of eighteen fixed baud rates, a 16X
clock derived from a programmable counter/timer, or an external 1X
or 16X clock. The baud rate generator and counter/timer can
operate directly from a crystal or from external clock inputs. The
ability to independently program the operating speed of the receiver
and transmitter make the QUART particularly attractive for
dual-speed channel applications such as clustered terminal
systems.
Each receiver is buffered with eight character FIFOs (first-in-first-out
memories) and one shift register to minimize the potential for
receiver overrun and to reduce interrupt overhead in interrupt driven
systems. In addition, a handshaking capability is provided to disable
a remote UART transmitter when the receiver buffer is full. (RTS
control)
The 2694 provides a power-down mode in which the oscillator is
stopped and the register contents are stored. This results in reduced
power consumption on the order of several magnitudes. The
QUART is fully TTL compatible and operates from a single +5V
power supply.
FEATURES
New low overhead interrupt control
Four Philips Semiconductors industry-standard UARTs
Eight byte receive FIFO and eight byte transmit FIFO for each
UART
Programmable data format:
5 to 8 data bits plus parity
Odd, even, no parity or force parity
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
Baud rate for the receiver and transmitter selectable from:
23 fixed rates: 50 to 230.4K baud Non-standard rates to 1.0M
baud
User-defined rates from the programmable counter/timer
associated with each of two blocks
External 1x or 16x clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
PIN CONFIGURATIONS
VCC
A5:0
CEN
RDN
WRN
D7-0
RESET
X1/CLK
X2
RDa-d
DACKN
IACKN
RQN
I/O0a–d
I/O1a–d
I/O2a–d
I/O3a–d
TDa-d
VSS
SD00158
Programmable channel mode
Normal (full-duplex), automatic echo, local loop back, remote
loopback
Programmable interrupt priorities
Identification of highest priority interrupt
Global interrupt register set provides data from interrupting
channel
Vectored interrupts with programmable vector format
IACKN and DTACKN signals
Built-in baud rate generator with choice of 18 rates
Four I/O pins per UART for modem controls, clocks, etc.
Power down mode
High-speed CMOS technology
52-pin PLCC and 48-pin DIP
Commercial and industrial temperature ranges available
On-chip crystal oscillator
TTL compatible
Single +5V power supply with low power mode
Two multifunction programmable 16-bit counter/timers
1MHz 16x mode operation
30ns data bus release time
“Watch Dog” timer for each receiver
ORDERING INFORMATION
PACKAGES
48-Pin Plastic Dual In-Line Package (DIP)
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
COMMERCIAL
VCC = +5V +10%,
TA = 0oC to +70oC
SC26C94C1N
SC26C94C1A
INDUSTRIAL
VCC = +5V +10%,
TA = –40oC to +85oC
SC26C94A1N
SC26C94A1A
DWG #
SOT240-1
SOT238-3
1995 May 1
1 853-1471 15179

1 page




SC26C94C1N pdf
Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC26C94
Table 1. QUART Registers1
A5:0
READ (RDN = Low)
000000
Mode Register a (MR0a, MR1a, MR2a)
000001
Status Register a (SRa)
000010
Reserved
000011
Receive Holding Register a (RxFIFOa)
000100
Input Port Change Reg ab (IPCRab)
000101
Interrupt Status Reg ab (ISRab)
000110
Counter/Timer Upper ab (CTUab)
000111
Counter/Timer Lower ab (CTLab)
001000
Mode Register b (MR0b, MR1b, MR2b)
001001
Status Register b (SRb)
001010
Reserved
001011
Receive Holding Register b (RxFIFOb)
001100
Output Port Register ab (OPRab)
001101
Input Port Register ab (IPRab)
001110
Start Counter ab
001111
Stop Counter ab
010000
Mode Register c (MR0c, MR1c, MR2c)
010001
Status Register c (SRc)
010010
Reserved
010011
Receive Holding Register c (RxFIFOc)
010100
Input Port Change Reg cd (IPCRcd)
010101
Interrupt Status Reg cd (ISRcd)
010110
Counter/Timer Upper cd (CTUcd)
010111
Counter/Timer Lower cd (CTLcd)
011000
Mode Register d (MR0d, MR1d, MR2d)
011001
Status Register d (SRd)
011010
Reserved
011011
Receive Holding Register d (RxFIFOd)
011100
Output Port Register cd (OPRcd)
011101
Input Port Register cd (IPRcd)
011110
Start Counter cd
011111
Stop Counter cd
100000
Bidding Control Register a (BCRa)
100001
Bidding Control Register b (BCRb)
100010
Bidding Control Register c (BCRc)
100011
Bidding Control Register d (BCRd)
100100
Reserved
100101
Reserved
100110
Reserved
100111
Reserved
101000
Current Interrupt Register (CIR)
101001
Global Interrupting Channel Reg (GICR)
101010
Global Int Byte Count Reg (GIBCR)
101011
Global Receive Holding Reg (GRxFIFO)
101100
Interrupt Control Register (ICR)
101101
Reserved
101110
Reserved
101111
Reserved
110000–111000 Reserved
111001
Test Mode
111010–111111 Reserved
WRITE (WRN = Low)
Mode Register a (MR0a, MR1a, MR2a)
Clock Select Register a (CSRa)
Command Register a (CRa)
Transmit Holding Register a (TxFIFOa)
Auxiliary Control Reg ab (ACRab)
Interrupt Mask Reg ab (IMRab)
Counter/Timer Upper Reg ab (CTURab)
Counter/Timer Lower Reg ab (CTLRab)
Mode Register b (MR0b, MR1b, MR2b)
Clock Select Register b (CSRb)
Command Register b (CRb)
Transmit Holding Register b (TxFIFOb)
Output Port Register ab (OPRab)
I/OPCRa (I/O Port Control Reg a)
I/OPCRb (I/O Port Control Reg b)
Reserved
Mode Register c (MR0c, MR1c, MR2c)
Clock Select Register c (CSRc)
Command Register c (CRc)
Transmit Holding Register c (TxFIFOc)
Auxiliary Control Reg cd (ACRcd)
Interrupt Mask Reg cd (IMRcd)
Counter/Timer Upper Reg cd (CTURcd)
Counter/Timer Lower Reg cd (CTLRcd)
Mode Register d (MR0d, MR1d, MR2d)
Clock Select Register d (CSRd)
Command Register d (CRd)
Transmit Holding Register d (TxFIFOd)
Output Port Register cd (OPRcd)
I/OPCRc (I/O Port Control Reg c)
I/OPCRd (I/O Port Control Reg d)
Reserved
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Power Down
Power Up
Disable DACKN
Enable DACKN
Reserved
Interrupt Vector Register (IVR)
Update CIR
Global Transmit Holding Reg (GTxFIFO)
Interrupt Control Register (ICR)
BRG Rate. 00 = low; 01 = high
Set X1/CLK divide by two2
Set X1/CLK Normal2
Reserved
Test Mode
Reserved
1995 May 1
5

5 Page





SC26C94C1N arduino
Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC26C94
Interrupt Context
The channel number of the winning “bid” is used by the address
decoders to provide data from the interrupting UART channel via a
set of Global pseudo-registers. The interrupt Global
pseudo-registers are:
1. Global Interrupting Byte Count
2. Global Interrupting Channel
3. Global Receive Holding Register
4. Global Transmit Holding Register
The first two Global “registers” are provided by Current Interrupt
Register fields as shown in Figure 5. The interrupting channel
number latched in CIR modifies address decoding so that the
Receive or Transmit Holding Register for the interrupting channel is
accessed during I/O involving the Global Receive and Transmit
Holding Registers. Similarly, for data interrupts from the transmitter
and receiver, the number of characters available for transfer to the
CPU or the number of transmit FIFO positions open is available by
reading the Global Interrupt Byte Count Register. For non-data
interrupts, a read of the Global Interrupt Byte Count Register yields
a value equal to the highest programmable filed.
In effect, once latched by an IACK or the Update CIR command, the
winning interrupt channel number determines the contents of the
global registers. All Global registers will provide data from the
interrupting UART channel.
Interrupt Threshold Calculation
The state of IRQN is determined by comparison of the winning “bid”
value to the Interrupt Threshold field of the Interrupt Control
Register.
The logic of the bidding circuit is such that when no interrupt source
has a value greater than the interrupt threshold then the interrupt is
not asserted and the CIR (Current Interrupt Register) is set to all
ones. When one or more of the 18 interrupt sources which are
enabled via the IMR (Interrupt Mask Register) exceed the threshold
then the interrupt threshold is effectively disconnected from the
bidding operation while the 18 sources now bid against each other.
The final result is that the highest bidding source will disable all
others and its value will be loaded to the CIR and the IRQN pin
asserted low. This all occurs during each cycle of the X1, X2 crystal
clock.
Table 2. Receiver FIFO Interrupt Fill Level
MR0[6]
0
0
1
1
MR1[6]
0
1
0
1
Interrupt Condition
1 or more bytes in FIFO (Rx RDY) default*
3 or more bytes in FIFO
6 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
Table 3. Receiver FIFO Interrupt Fill Level
MR0[5]
0
0
1
1
MR0[4]
0
1
0
1
Interrupt Condition
8 bytes empty (Tx EMPTY) default*
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty (Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is competely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
*These conditions, for interrupt purposes, make the RxFIFO look
like a 3 byte FIFO; the TxFIFO a 1 byte FIFO. This is to allow
software compatibility with previous Philips UART devices. Both
FIFOs accept 8 bytes of data regardless of this bit setting. Only the
interrupt is affected.
INTERRUPT NOTE ON 26C94:
For the receivers and transmitters, the bidding of any particular
unit may be held off unless one of four FIFO fill levels is
attained. This is done by setting the RxINT and TxINT bits in
MR0 and MR1 to non-zero values. This may be used to prevent
a receiver or transmitter from generating an interrupt even
though it is filed above the bid threshold. Although this is not
in agreement with the idea that each enabled interrupt source
bid with equal authority, it does allow the flexibility of giving
particular receiver or transmitters more interrupt importance
than others.
This may be used when the Interrupt Threshold is set at or
above 100000. Note than in this case the transmitter cannot
generate an interrupt. If the interrupt threshold MSBs were set
to 011 and the ‘Receiver Interrupt Bits’ on the MR registers set
to a value other than 00 then the RxFIFO could not generate
and interrupt until it had 4, 6 or 8 bytes. This in effect partially
defeats the hardwired characteristic that the receiver interrupts
should have more importance than the transmitter. This
characteristic has been implemented by setting the MSB of the
transmitter bid to zero.
Vectored Interrupts
The QUART responds to an Interrupt Acknowledge (IACK) initiated
by the host by providing an Interrupt Acknowledge Vector on D7:0.
The interrupt acknowledge cycle is terminated with a DACKN pulse.
The vector provided by the QUART can have one of the three forms
under control of the IVC control field (bits 1:0 of the Interrupt Control
Register):
With IVC = 00 (IVR only)
IVR7:0
8
With IVC = 01 (channel number)
IVR7:2
6
With IVC = 10 (type & channel number)
IVR7:5
3
Type
3
Chan #
2
Chan #
2
SD00163
A code of 11 in the Interrupt Vector Control Field of the ICR results
in NO interrupt vector being generated. The external data bus is
driven to a high impedance throughout the IACK cycle. A DACKN
will be generated normally for the IACK cycle, however.
NOTE: If IACKN is not being used then the command “UPDATE
CIR” must be issued for the global and interrupt registers to be
updated.
PROGRAMMING UART CONTROL REGISTERS
The operation of the QUART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is described in Table 1.
The bit formats of the QUART registers are depicted in Table 2.
1995 May 1
11

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