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Número de pieza SC16C754IA68
Descripción Quad UART with 64-byte FIFO
Fabricantes NXP Semiconductors 
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SC16C754
Quad UART with 64-byte FIFO
Rev. 04 — 19 June 2003
Product data
1. Description
The SC16C754 is a quad universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbits/s (3.3 V and 5 V). The SC16C754 offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C754 is available in plastic LQFP80 and PLCC68 packages.
2. Features
s Pin compatible with SC16C654IA68 and SC16C554IA68 with additional
enhancements
s Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbits/s)
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s Software/hardware flow control
x Programmable Xon/Xoff characters
x Programmable auto-RTS and auto-CTS
s Optional data flow resume by Xon any character
s DMA signalling capability for both received and transmitted data
s Supports 5 V, 3.3 V and 2.5 V operation
s Software selectable baud rate generator

1 page




SC16C754IA68 pdf
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
handbook, full pagewidth
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
SC16C754IA68
60 DSRD
59 CDSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
002aaa367
Fig 3. PLCC68 pin configuration.
5.2 Pin description
Table 2: Pin description
Symbol
Pin
Type
LQFP80 PLCC68
A0 30 34 I
A1 29 33 I
A2 28 32 I
CDA, CDB,
CDC, CDD
79, 23, 9, 27, I
39, 63 43, 61
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Carrier Detect (Active-LOW). These inputs are associated with individual
UART channels A through D. A logic LOW on these pins indicates that a
carrier has been detected by the modem for that channel. The state of these
inputs is reflected in the modem status register (MSR).
9397 750 11618
Product data
Rev. 04 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 49

5 Page





SC16C754IA68 arduino
Philips Semiconductors
SC16C754
Quad UART with 64-byte FIFO
Table 3: Software flow control options (EFR[0:3])…continued
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow controls
X X 0 0 no receive flow control
X X 1 0 receiver compared Xon1, Xoff1
X X 0 1 receiver compares Xon2, Xoff2
1 0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
1 1 1 1 transmit Xon1, Xon2, Xoff1, Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Remark: When using software flow control, the Xon/Xoff characters cannot be used
for data characters.
There are two other enhanced features relating to software flow control:
Xon Any function (MCR[5]): Operation will resume after receiving any character
after recognizing the Xoff character. It is possible that an Xon1 character is
recognized as an Xon Any character, which could cause an Xon2 character to be
written to the RX FIFO.
Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The
Xoff interrupt is cleared by a read of the IIR. The special character is transferred to
the RX FIFO.
6.3.1 RX
When software flow control operation is enabled, the SC16C754 will compare
incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2
must be received sequentially). When the correct Xoff character are received,
transmission is halted after completing transmission of the current character. Xoff
detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go HIGH.
To resume transmission, an Xon1,2 character must be received (in certain cases
Xon1 and Xon2 must be received sequentially). When the correct Xon characters are
received, IIR[4] is cleared, and the Xoff interrupt disappears.
6.3.2 TX
Xoff1/2 character is transmitted when the RX FIFO has passed the HALT trigger level
programmed in TCR[3:0].
Xon1/2 character is transmitted when the RX FIFO reaches the RESUME trigger
level programmed in TCR[7:4].
The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of
an ordinary byte from the FIFO. This means that even if the word length is set to be 5,
6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be
transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom
done, but this functionality is included to maintain compatibility with earlier designs.)
9397 750 11618
Product data
Rev. 04 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 49

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