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PDF SC16C752BIB48 Data sheet ( Hoja de datos )

Número de pieza SC16C752BIB48
Descripción 5 V/ 3.3 V and 2.5 V dual UART/ 5 Mbit/s (max.)/ with 64-byte FIFOs
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with
64-byte FIFOs
Rev. 03 — 14 December 2004
Product data
1. Description
The SC16C752B is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to
5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software flow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can
detect FIFO underflow. The UART also contains a software interface for modem
control operations, and has software flow control and hardware flow control
capabilities.
The SC16C752B is available in plastic LQFP48 and HVQFN32 packages.
2. Features
s Dual channel
s Pin compatible with SC16C2550 with additional enhancements
s Up to 5 Mbit/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbit/s)
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s Software/hardware flow control
x Programmable Xon/Xoff characters
x Programmable auto-RTS and auto-CTS
s Optional data flow resume by Xon any character
s DMA signalling capability for both received and transmitted data
s Supports 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs

1 page




SC16C752BIB48 pdf
Philips Semiconductors
SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
5.2 Pin description
Table 2: Pin description
Symbol
Pin
Type
LQFP48 HVQFN32
A0
28 19
I
A1
27 18
I
A2
26 17
I
CDA, CDB 40, 16 -
I
CSA, CSB 10, 11 8, 9
I
CTSA,
CTSB
38, 23 25, 16
I
D0-D4,
D5-D7
DSRA,
DSRB
44-48, 27-31, 32, I/O
1-3 1-2
39, 20 -
I
DTRA,
DTRB
34, 35 -
O
GND
17
INTA, INTB 30, 29
13
21, 20
I
O
IOR 19 14
IOW 15 12
I
I
n.c. 12, 24, -
25, 37
-
Description
Address 0 select bit. Internal registers address selection.
Address 1 select bit. Internal registers address selection.
Address 2 select bit. Internal registers address selection.
Carrier Detect (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic LOW on these pins indicates that a carrier
has been detected by the modem for that channel. The state of these inputs
is reflected in the modem status register (MSR).
Chip Select (Active-LOW). These pins enable data transfers between the
user CPU and the SC16C752B for the channel(s) addressed. Individual
UART sections (A, B) are addressed by providing a logic LOW on the
respective CSA and CSB pins.
Clear to Send (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic 0 (LOW) on the CTS pins indicates the
modem or data set is ready to accept transmit data from the SC16C752B.
Status can be tested by reading MSR[4]. These pins only affect the transmit
and receive operations when Auto-CTS function is enabled via the Enhanced
Feature Register EFR[7] for hardware flow control operation.
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data stream.
Data Set Ready (Active-LOW). These inputs are associated with individual
UART channels A and B. A logic 0 (LOW) on these pins indicates the modem
or data set is powered-on and is ready for data exchange with the UART. The
state of these inputs is reflected in the modem status register (MSR).
Data Terminal Ready (Active-LOW). These outputs are associated with
individual UART channels A and B. A logic 0 (LOW) on these pins indicates
that the SC16C752B is powered-on and ready. These pins can be controlled
via the modem control register. Writing a logic 1 to MCR[0] will set the DTR
output to logic 0 (LOW), enabling the modem. The output of these pins will
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
Signal and power ground.
Interrupt A and B (Active-HIGH). These pins provide individual channel
interrupts INTA and INTB. INTA and INTB are enabled when MCR[3] is set to
a logic 1, interrupt sources are enabled in the interrupt enable register (IER).
Interrupt conditions include: receiver errors, available receiver buffer data,
available transmit buffer space, or when a modem status flag is detected.
INTA, INTB are in the high-impedance state after reset.
Input/Output Read strobe (Active-LOW). A HIGH-to-LOW transition on
IOR will load the contents of an internal register defined by address bits
A0-A2 onto the SC16C752B data bus (D0-D7) for access by external CPU.
Input/Output Write strobe (Active-LOW). A LOW-to-HIGH transition on
IOW will transfer the contents of the data bus (D0-D7) from the external CPU
to an internal register that is defined by address bits A0-A2 and CSA and
CSB.
Not connected.
9397 750 14443
Product data
Rev. 03 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 47

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SC16C752BIB48 arduino
Philips Semiconductors
SC16C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.3.3 Software flow control example
UART1
UART2
TRANSMIT FIFO
RECEIVE FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
data
Xoff–Xon–Xoff
SERIAL-TO-PARALLEL
PARALLEL-TO-SERIAL
Xon-1 WORD
Xon-1 WORD
Xon-2 WORD
Xon-2 WORD
Xoff-1 WORD
Xoff-1 WORD
Xoff-2 WORD
compare
programmed
Xon-Xoff
characters
Xoff-2 WORD
002aaa229
Fig 7. Software flow control example.
Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are
using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both
have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to
32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52.
UART 1 begins transmission and sends 52 characters, at which point UART2 will
generate an interrupt to its processor to service the RCV FIFO, but assume the
interrupt latency is fairly long. UART1 will continue sending characters until a total of
60 characters have been sent. At this time, UART2 will transmit a 0F to UART1,
informing UART1 to halt transmission. UART1 will likely send the 61st character while
UART2 is sending the Xoff character. Now UART2 is serviced and the processor
reads enough data out of the RX FIFO that the level drops to 32. UART2 will now
send a 0D to UART1, informing UART1 to resume transmission.
9397 750 14443
Product data
Rev. 03 — 14 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 47

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