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PDF SC16C750BIBS Data sheet ( Hoja de datos )
| Número de pieza | SC16C750BIBS | |
| Descripción | 5 V/ 3.3 V and 2.5 V UART with 64-byte FIFOs | |
| Fabricantes | NXP Semiconductors | |
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SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Rev. 03 — 13 December 2004
Product data
1. General description
The SC16C750B is a Universal Asynchronous Receiver and Transmitter (UART)
used for serial data communications. Its principal function is to convert parallel data
into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C750B is pin compatible with the TL16C750 and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C750B. Some of these added features are the 64-byte
receive and transmit FIFOs, automatic hardware flow control. The selectable
auto-flow control feature significantly reduces software overload and increases
system efficiency while in FIFO mode by automatically controlling serial data flow
using RTS output and CTS input signals. The SC16C750B also provides DMA mode
data transfers through FIFO trigger levels and the TXRDY and RXRDY signals.
On-board status registers provide the user with error indications, operational status,
and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The SC16C750B operates at 5 V, 3.3 V and 2.5 V, the industrial temperature range
and is available in plastic PLCC44, LQFP64, and HVQFN32 packages.
2. Features
s Single channel
s 5 V, 3.3 V and 2.5 V operation
s 5 V tolerant inputs
s Industrial temperature range (−40 °C to +85 °C)
s After reset, all registers are identical to the typical 16C450 register set
s Capable of running with all existing generic 16C450 software
s Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with SC16C750 and TL16C750
s Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at
2.5 V
s 64 byte transmit FIFO
s 64 byte receive FIFO with error flags
s Programmable auto-RTS and auto-CTS
x In auto-CTS mode, CTS controls transmitter
x In auto-RTS mode, RxFIFO contents and threshold control RTS
s Automatic hardware flow control
s Software selectable Baud Rate Generator
s Four selectable Receive interrupt trigger levels
1 page  
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
XTAL1 1
XTAL2 2
n.c. 3
IOW 4
n.c. 5
IOW 6
n.c. 7
GND 8
IOR 9
IOR 10
n.c. 11
DDIS 12
TXRDY 13
n.c. 14
AS 15
n.c. 16
SC16C750BIB64
48 D4
47 n.c.
46 D3
45 D2
44 n.c.
43 D1
42 D0
41 n.c.
40 VCC
39 n.c.
38 RI
37 n.c.
36 DCD
35 DSR
34 n.c.
33 CTS
002aaa590
Fig 4. LQFP64 pin configuration.
5.2 Pin description
Table 2:
Symbol
A2-A0
Pin description
Pin
PLCC44 LQFP64
29, 30, 17, 18, 20
31
AS 28 15
BAUDOUT 17
64
Type
HVQFN32
16, 17, 18 I
-I
8O
Description
Register select. A0-A2 are used during read and write operations
to select the UART register to read from or write to. Refer to Table 3
for register addresses and refer to AS description.
Address strobe. When AS is active (LOW), A0, A1, and A2 and
CS0, CS1, and CS2 drive the internal select logic directly; when AS
is HIGH, the register select and chip select signals are held at the
logic levels they were in when the LOW-to-HIGH transition of AS
occurred.
Baud out. BAUDOUT is a 16× clock signal for the transmitter
section of the UART. The clock rate is established by the reference
oscillator frequency divided by a divisor specified in the baud
generator divisor latches. BAUDOUT may also be used for the
receiver section by tying this output to RCLK.
9397 750 14453
Product data
Rev. 03 — 13 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 44
5 Page 
Philips Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
6.3 Hardware flow control
When automatic hardware flow control is enabled, the SC16C750B monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting MCR[5] (RTS) and
MCR[1] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, the SC16C750B will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out. Transmission is resumed after the
CTS input returns to a logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is emptied. However, under the
above described conditions, the SC16C750B will continue to accept data until the
receive FIFO is full.
6.4 Time-out interrupts
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C750B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
9397 750 14453
Product data
Rev. 03 — 13 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 44
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