PDF SC16C2552IA44 Data sheet ( Hoja de datos )

Número de pieza	SC16C2552IA44
Descripción	Dual UART with 16-byte transmit and receive FIFOs
Fabricantes	NXP Semiconductors
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No Preview Available ! SC16C2552 Dual UART with 16-byte transmit and receive FIFOs Rev. 03 — 20 June 2003 Product data 1. Description The SC16C2552 is a two channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data, and vice versa. The UART can handle serial data rates up to 5 Mbits/s. The SC16C2552 is pin compatible with the PC16C552 and ST16C2552. It will power-up to be functionally equivalent to the 16C2450. The SC16C2552 provides enhanced UART functions with 16 byte FIFOs, modem control interface, DMA mode data transfer and concurrent writes to control registers of both channels. The DMA mode data transfer is controlled by the FIFO trigger levels and the RXRDY and TXRDY signals. On-board status registers provide the user with error indications and operational status. System interrupts and modem control features may be tailored by software to meet speciﬁc user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2552 operates at 5 V, 3.3 V and 2.5 V, and the Industrial temperature range, and is available in a plastic PLCC44 package. 2. Features s Industrial temperature range (−40 °C to +85 °C) s 5 V, 3.3 V and 2.5 V operation s Pin-to-pin and functionally compatible to PC16C552, ST16C2552 s Software compatible with INS8250, NS16C550 s Up to 5 Mbits/s data rate at 5 V and 3 V, and 3 Mbits/s at 2.5 V s 16-byte transmit FIFO s 16-byte receive FIFO with error ﬂags s Independent transmit and receive UART control s Four selectable Receive FIFO interrupt trigger levels; ﬁxed XMIT FIFO interrupt trigger level s Modem control signals (CTS, RTS, DSR, DTR, RI, CD) s DMA operation and DMA monitoring via package I/O pins, TXRDY/RXRDY s UART internal register sections A and B may be written to concurrently s Multi-function output allows more package functions with fewer I/O pins s Programmable character lengths (5, 6, 7, 8), with even, odd, or no parity 1 page Philips Semiconductors SC16C2552 Dual UART with 16-byte transmit and receive FIFOs Table 2: Pin description…continued Symbol Pin Type Description CTSA, CTSB 40, 28 I Clear to Send (Active-LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C2552. Status can be tested by reading MSR[4]. DSRA, DSRB 41, 29 I Data Set Ready (Active-LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. DTRA, DTRB 37, 27 O Data Terminal Ready (Active-LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates that the SC16C2552 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. RIA, RIB 43, 31 I Ring Indicator (Active-LOW). These inputs are associated with individual UART channels, A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. RTSA, RTSB 36, 23 O Request to Send (Active-LOW). These outputs are associated with individual UART channels, A through B. A logic 0 on the RTS pin indicates the receiver is ready to receive data. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating that the receiver is ready to receive data. After a reset this pin will be set to a logic 1. RXA, RXB 39, 25 I Receive data A, B. These inputs are associated with individual serial channel data to the SC16C2552 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input, internally. TXA, TXB 38, 26 O Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C2552. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. 9397 750 11636 Product data Rev. 03 — 20 June 2003 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 5 of 38 5 Page Philips Semiconductors SC16C2552 Dual UART with 16-byte transmit and receive FIFOs SC16C2552 D0–D7 IOR IOW RESET DATA BUS AND CONTROL LOGIC A0–A2 CS CHSEL REGISTER SELECT LOGIC INTA, INTB TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC Fig 4. Internal loop-back mode diagram. TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TXA, TXB MCR[4] = 1 RECEIVE FIFO REGISTERS CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RECEIVE SHIFT REGISTER RXA, RXB MODEM CONTROL LOGIC RTSA, RTSB DSRA, DSRB DTRA, DTRB CTSA, CTSB OP1A, OP1B RIA, RIB OP2A, OP2B CDA, CDB 002aaa126 9397 750 11636 Product data Rev. 03 — 20 June 2003 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 11 of 38 11 Page

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