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PDF SC16C2550IB48 Data sheet ( Hoja de datos )
| Número de pieza | SC16C2550IB48 | |
| Descripción | Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder | |
| Fabricantes | NXP Semiconductors | |
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SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs
and infrared (IrDA) encoder/decoder
Rev. 03 — 19 June 2003
Product data
1. Description
The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s.
The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and
RXRDY signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loop-back capability allows
on-board diagnostics. Independent programmable baud rate generators are provided
to select transmit and receive baud rates.
The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.
2. Features
s 2 channel UART
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range
s Pin and functionally compatible to 16C2450 and software compatible with
INS8250, SC16C550
s Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V
s 16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU
s 16 byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
s Independent transmit and receive UART control
s Four selectable Receive FIFO interrupt trigger levels
s Automatic software/hardware flow control
s Programmable Xon/Xoff characters
s Software selectable Baud Rate Generator
s Sleep mode
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled
1 page  
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
D5 7
D6 8
D7 9
RXB 10
RXA 11
TXRDYB 12
TXA 13
TXB 14
OP2B 15
CSA 16
CSB 17
SC16C2550IA44
Fig 3. PLCC44 pin configuration.
39 RESET
38 DTRB
37 DTRA
36 RTSA
35 OP2A
34 RXRDYA
33 INTA
32 INTB
31 A0
30 A1
29 A2
002aaa103
9397 750 11621
Product data
Rev. 03 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 46
5 Page 
Philips Semiconductors
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
encoder/decoder
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
Table 5: Flow control mechanism
Selected trigger level
(characters)
INT pin activation
11
44
88
14 14
Negate RTS or
send Xoff
4
8
12
14
Assert RTS or
send Xon
1
4
8
10
6.4 Hardware flow control
When automatic hardware flow control is enabled, the SC16C2550 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C2550 will continue to accept data until the receive FIFO is full.
9397 750 11621
Product data
6.5 Software flow control
When software flow control is enabled, the SC16C2550 compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C2550 will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C2550 will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C2550 will resume operation and
clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
Rev. 03 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 46
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| PDF Descargar | [ Datasheet SC16C2550IB48.PDF ] | |
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