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Número de pieza SC1405TS.TR
Descripción HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER
Fabricantes Semtech Corporation 
Logotipo Semtech Corporation Logotipo



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HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
SC1405
August 31, 2000
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1405 is a Dual-MOSFET Driver with an internal
Overlap Protection Circuit to prevent shoot-through
from VIN to GND in the main switching and syn-
chronous MOSFET’s. Each driver is capable of driving
a 3000pF load in 20ns rise/fall time and has ULTRA-
FAST propagation delay from input transition to the
gate of the power FET’s. The Overlap Protection circuit
ensures that the second FET does not turn on until the
top FET source has reached a voltage low enough to
prevent shoot-through. The delay between the bottom
gate going low to the top gate transitioning to high is
externally programmable via a capacitor for optimal
reduction of switching losses at the operating fre-
quency. The bottom FET may be disabled at light loads
by keeping S_MOD low to trigger asynchronous opera-
tion, thus saving the bottom FET’s gate drive current
and inductor ripple current. An internal voltage refer-
ence allows threshold adjustment for an Output Over-
Voltage protection circuitry, independent of the PWM
feedback loop. Under-Voltage-Lock-Out circuit is in-
cluded to guarantee that both driver outputs are low
when the 5V logic level is less than or equal to 4.4V
(typ) at supply ramp up (4.35V at supply ramp down). A
CMOS output provides status indication of the 5V sup-
ply. A low enable input places the IC in stand-by mode
thereby reducing supply current to less than 10µA.
SC1405 is offered in a high pitch (.025” lead spacing)
TSSOP package.
PIN CONFIGURATION
FEATURES
= Fast rise and fall times (20ns typical with 3000pf
load)
= 20ns max. Propagation delay (BG going low)
= Adaptive/programmable shoot-through protection
= Wide input voltage range (4.5-25V)
= Programmable delay between MOSFET’s
= Power saving asynchronous mode control
= Output overvoltage protection/overtemp shutdown
= Under-Voltage lock-out and power ready signal
= Less than 10µA stand-by current (EN=low)
= Power ready output signal
APPLICATIONS
= High Density/Fast transient power supplies
= Motor Drives/Class-D amps
= High frequency (to 1.2 MHz) operation allows use
of small inductors and low cost caps in place of
electrolytics
= Portable computers
ORDERING INFORMATION
DEVICE(1)
PACKAGE TEMP. RANGE (TJ)
SC1405TS.TR TSSOP-14
0 - 125°C
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
BLOCK DIAGRAM
Top View
(14-Pin TSSOP)
© 2000 SEMTECH CORP.
1
652 MITCHELL ROAD NEWBURY PARK CA 91320

1 page




SC1405TS.TR pdf
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
SC1405
August 31, 2000
PIN DESCRIPTION
Pin #
1
Pin Name
OVP_S
2 EN
3 GND
4 CO
5 S_MOD
6 DELAY_C
7 PRDY
8 VCC
9 BG
10 PGND
11 DSPS_DR
12 DRN
13 TG
14 BST
Pin Function
Overvoltage protection sense. External scaling resistors required to set
protection threshold.
When high, this pin enables the internal circuitry of the device. When
low, TG, BG and PRDY are forced low and the supply current (5V) is
less than 10µA.
Logic GND.
TTL-level input signal to the MOSFET drivers.
When low, this signal forces BG to be low. When high, BG is not a
function of this signal.
Sets the additional propagation delay for BG going low to TG going high.
Total propagation delay= 20ns + 1ns/pF.
This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this
output is driven low. When 5V is greater than or equals to 4.4V(typ) this
output is driven to 5V level. This output has a 10mA drive capability and
10µA sink capability.
+5V supply. A .22-1µF ceramic capacitor should be connected from 5V
to PGND very close to this pin.
Output drive for the synchronous MOSFET.
Power ground. Connect to the synchronous FET power ground.
Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD
is high, this pin follows the BG driver pin voltage.
This pin connects to the junction of the switching and synchronous
MOSFET’s. This pin can be subjected to a -2V minimum relative to
PGND without affecting operation.
Output gate drive for the switching (high-side) MOSFET.
Bootstrap pin. A capacitor is connected between BST and DRN pins to
develop the floating bootstrap voltage for the high-side MOSFET. The
capacitor value is typically between 0.1µF and 1µF (ceramic).
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
PIN CONFIGURATION
© 2000 SEMTECH CORP.
5
652 MITCHELL ROAD NEWBURY PARK CA 91320

5 Page





SC1405TS.TR arduino
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
August 31, 2000
Performance diagrams, Application Evaluation Board. (Fig.3)
SC1405
Figure 4-Timing diagram:
Ch1:CO input
Ch2:TG drive
Ch3:BG non-overlap drive
Ch4:phase node
Iout=20A (10A/phase)
Refer to Eval. Schematic
(fig.3)
Figure 5-Timing diagram:
Rise/Fall times
Ch1:TG drive
Ch2:BG drive
Cursor:TpdhTG
Iout=20A (10A/phase)
Refer to Eval. Schematic
(fig.3)
Vin=10V, Vout=2V TOP FET IR7811, Bottom
FET IR7030(L) Qg(tot)=35nc
© 2000 SEMTECH CORP.
11
652 MITCHELL ROAD NEWBURY PARK CA 91320

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