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PDF K9K1G08U0M-YCB0 Data sheet ( Hoja de datos )
| Número de pieza | K9K1G08U0M-YCB0 | |
| Descripción | 128M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
Document Title
128M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No History
0.0 1. Initial issue
0.1 1.[Page 31] device code (76h) --> device code (79h)
0.2 1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
Draft Date Remark
Apr. 7th 2001
Jul. 3rd 2001
Jul. 23th 2001
2.5V
VCC
High
WP
2.5V
WE 1µ
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. [Page28] Only address A 14 to A25 is valid while A9 to A13 is ignored
--> Only address A14 to A26 is valid while A 9 to A13 is ignored
0.3 (page 30)
A14 and A15 must be the same between source and target page
Sep. 13th 2001
--> A14 , A15 and A26 must be the same between source and target page
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
Memory Map
The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows
it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is
configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory
array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohib-
ited.
Figure 3. Memory Array Map
Plane 0
(1024 Block)
Block 0
Page 0
Page 1
Plane 1
(1024 Block)
Block 1
Page 0
Page 1
Plane 2
(1024 Block)
Block 2
Page 0
Page 1
Plane 3
(1024 Block)
Block 3
Page 0
Page 1
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Page 30
Page 31
Block 4092
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Plane 4
(1024 Block)
Block 4096
Page 0
Page 1
Page 30
Page 31
Block 4093
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Plane 5
(1024 Block)
Block 4097
Page 0
Page 1
Page 30
Page 31
Block 4094
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Plane 6
(1024 Block)
Block 4098
Page 0
Page 1
Page 30
Page 31
Block 4095
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Plane 7
(1024 Block)
Block 4099
Page 0
Page 1
Page 30
Page 31
Block 8188
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Block 8189
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Block 8190
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
Block 8191
Page 0
Page 1
Page 30
Page 31
528byte Page Registers
5
5 Page 
K9K1G08U0M-YCB0, K9K1G08U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the ac tual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail-
ure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of mem-
ory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Write
Read
Failure Mode
Erase Failure
Program Failure
Single Bit Failure
Detection and Countermeasure sequence
Status Read after Erase --> Block Replacement
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
Start
Write 80h
Write Address
If ECC is used, this verification
operation is not needed.
Write 00h
Write Address
Write Data
Write 10h
Wait for tR Time
Verify Data
*
No
Program Error
Read Status Register
* No
Program Error
I/O 6 = 1 ?
or R/B = 1 ?
Yes
I/O 0 = 0 ?
No
Yes
Program Completed
* : If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
Yes
11
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| Páginas | Total 30 Páginas | |
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