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PDF K9K1216U0C Data sheet ( Hoja de datos )
| Número de pieza | K9K1216U0C | |
| Descripción | 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
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K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
Document Title
64M x 8 Bit , 32M x 16 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
Sep. 12th 2002
1.0 1.Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C
Jan. 3rd 2003
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 34)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 35)
4. Add the specification of Block Lock scheme.(Page 29~32)
5. Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
2.0 1. The Maximum operating current is changed.
Read : Icc1 20mA-->30mA
Program : Icc2 20mA-->40mA
Erase : Icc3 20mA-->40mA
Jan. 17th 2003
2.1 The min. Vcc value 1.8V devices is changed.
K9K12XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 5th 2003
2.2 Pb-free Package is added.
K9K1208U0C-HCB0,HIB0
K9K12XXQ0C-HCB0,HIB0
K9K1216U0C-HCB0,HIB0
K9K1216Q0C-HCB0,HIB0
Mar. 13rd 2003
2.3 Errata is added.(Front Page)-K9K12XXQ0C
tWC tWP tRC tREH tRP tREA tCEA
Specification 45 25 50 15 25 30 45
Relaxed value 60 40 60 20 40 40 55
Mar. 17th 2003
2.4 1. Max. Thickness of TBGA packge is changed.
0.09±0.10(Before) --> 1.10±0.10(After)
2. New definition of the number of invalid blocks is added.
Apr. 4th 2003
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
2.5
1. The guidence of LOCKPRE pin usage is changed.
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTO-
Jul. 4th 2003
READ, connect it Vss.(Before)
--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect
it Vss or leave it N.C(After)
2. 2.65V device is added.
3. Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
Remark
Advance
Preliminary
Preliminary
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
1 page  
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9K1208X0C)
I/O0 ~ I/O15
(K9K1216X0C)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
CLE The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
all blocks go to lock state.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected
LOCKPRE
LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
3.3V device(K9K12XXU0C)
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
5
5 Page 
K9K1208Q0C
K9K1208D0C
K9K1208U0C
K9K1216Q0C
K9K1216D0C
K9K1216U0C
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
NVB
Min
4026
Typ.
-
Max
4096
Unit
Blocks
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9K12XXX0C-GCB0,JCB0 :TA=0 to 70°C, K9K12XXX0C-GIB0,JCB0 :TA=-40 to 85°C
K9K12XXQ0C : Vcc=1.70V~1.95V , K9K12XXD0C : Vcc=2.4V~2.9V , K9K12XXU0C : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K12XXQ0C
K9K12XXD0C
K9K12XXU0C
Input Pulse Levels
0V to VccQ
0V to VccQ
0.4V to 2.4V
Input Rise and Fall Times
5ns 5ns
5ns
Input and Output Timing Levels
VccQ/2
VccQ/2
1.5V
K9K12XXQ0C:Output Load (VccQ:1.8V +/-10%)
K9K12XXD0C:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9K12XXU0C:Output Load (VccQ:3.0V +/-10%)
K9K12XXU0C:Output Load (VccQ:3.3V +/-10%)
-
- 1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
20
20
MODE SELECTION
CLE
ALE
CE
WE
RE LOCKPRE WP
Mode
HL L
LHL
H X X Read Mode Command Input
HXX
Address Input(4clock)
HL L
LHL
H X H Write Mode Command Input
HXH
Address Input(4clock)
LLL
H X H Data Input
L L LH
X X Data Output
X X X X H X X During Read(Busy) on the devices
X X X X X X H During Program(Busy)
X X X X X X H During Erase(Busy)
X X(1) X X X X L Write Protect
X X H X X 0V/VCC(2 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Unit
pF
pF
11
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