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PDF K9F8008W0M-TCB0 Data sheet ( Hoja de datos )
| Número de pieza | K9F8008W0M-TCB0 | |
| Descripción | 1M x 8 bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
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K9F8008W0M-TCB0, K9F8008W0M-TIB0
Document Title
1M x 8 bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
Draft Date
0.0 Data Sheet 1997
April 10th 1997
1.0 Data Sheet 1998
1. Changed tBERS parameter : 5ms(Typ.) → 2ms(Typ.)
10ms(Max.) → 4ms(Max.)
2. Changed tPROG parameter : 1.5ms(Max.) → 1.0ms(Max.)
April 10th 1998
1.1 Data sheet 1998
1. Cjanged DC and Operating Characteristics
July 14th 1998
Parameter
Vcc=2.7V~3.6V
Typ Max
Vcc=3.6V~5.5V
Typ Max
Unit
Burst Read
Operating
Current Program
Eraase
10 → 5
10 → 5
10 → 5
20 → 10
20 → 10
20 → 10
15 → 10
15 → 10
15 → 10
30 → 20
30 → 20
30 → 20
mA
Stand-by Current (CMOS) 5 → 10
50
10 100 → 50
Input Leakage Current
- 10 → ±10 - 10 → ±10 µA
Output Leakage Current
- 10 → ±10 - 10 → ±10
1.2 Data Sheet 1999
April 10th 1999
1) Added CE dont’ care mode during the data-loading and reading
1.3 1) Revised real-time map-out algorithm(refer to technical notes)
July 23th 1999
Changed device name
1.4 - KM29W8000T -> K9F8008W0M-TCB0
- KM29W8000IT -> K9F8008W0M-TIB0
Sep. 15th 1999
Remark
Advance
Preliminary
Final
Final
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
1 page  
K9F8008W0M-TCB0, K9F8008W0M-TIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the devices is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O0 ~ I/O7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or when outputs are disabled.
5
5 Page 
K9F8008W0M-TCB0, K9F8008W0M-TIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60H
Write 00H
Write Block Address
Write Address
Write D0H
Read Data
Write 70H
ECC Generation
SR. 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
SR. 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Block A
When the error happens in Block "A", try to write the
data into another Block "B" by reloading from an exter-
nal buffer. Then, prevent further system access to
Block "A"(by creating a "invalid block" table or other
appropriate scheme.)
Block B
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet K9F8008W0M-TCB0.PDF ] | |
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