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PDF K9F5608U0A-YCB0 Data sheet ( Hoja de datos )

Número de pieza K9F5608U0A-YCB0
Descripción 32M x 8 Bit NAND Flash Memory
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K9F5608U0A-YCB0,K9F5608U0A-YIB0
FLASH MEMORY
Document Title
32M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
Draft Date
July 17th 2000
0.1 1. Support copy-back program
Oct. 4th 2000
- The copy-back program is configured to quickly and efficiently rewrite
data stored in one page within the array to another page within the
same array without utilizing an external memory. Since the time-con
suming sequently-reading and its re-loading cycles are removed, the
system performance is improved. The benefit is especially obvious
when a portion of a block is updated so that the rest of the block also
need to be copied to the newly assigned free block.
0.2 1. Explain how pointer operation works in detail.
Nov. 20th 2000
2. For partial page programming into the copied page
- Once the copy-back Program is finished, any additional partial page
programming into the copied pages is prohibited before erase.
3. Renamed GND input (pin # 6) on behalf of SE (pin # 6)
- The SE input controls the access of the spare area. When SE is high,
the spare area is not accessible for reading or programming. SE is rec
ommended to be coupled to GND or Vcc and should not be toggled
during reading or programming.
=> Connect this input pin to GND or set to static low state unless the
sequential read mode excluding spare area is used.
4. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes into
Busy for maximum 5us.
0.3 1. In addition, explain WE function in pin description
- The WE must be held high when outputs are activated.
Mar. 2th 2001
0.4 1.Powerup sequence is added
Jul. 22th 2001
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
~ 2.5V
~ 2.5V
VCC
High
WP
WE
1µ
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 100ns --> 20ns
Remark
Advanced
Information
Preliminary
Preliminary
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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K9F5608U0A-YCB0 pdf
K9F5608U0A-YCB0,K9F5608U0A-YIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the Busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
GND (Pin # 6)
Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
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K9F5608U0A-YCB0 arduino
K9F5608U0A-YCB0,K9F5608U0A-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Status Register
Read Data
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
{1st
(n-1)th
nth
Block A
an error occurs.
(page)
{1st
(n-1)th
nth
(page)
Block B
2
Buffer memory of the controller.
1
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
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