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PDF K9F4008W0A-TCB0 Data sheet ( Hoja de datos )
| Número de pieza | K9F4008W0A-TCB0 | |
| Descripción | 512K x 8 bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K9F4008W0A-TCB0 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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K9F3208W0A-TCB0, K9F3208W0A-TIB0
Document Title
4M x 8 Bit NAND Flash Memory
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
0.1 Data Sheet, 1999
Draft Date
April 10th 1998
April 10th 1999
1. Added CE don’t care mode during the data-loading and reading
0.2 1. Revised real-time map-out algorithm(refer to technical notes)
2. Removed erase suspend/resume mode
July 23th 1999
0.3 1. Changed device name
- KM29W32000AT -> K9F3208W0A-TCB0
- KM29W32000AIT -> K9F3208W0A-TIB0
Sep. 15th 1999
0.4 1. Changed invalid block(s) marking method prior to shipping
July 17th 2000
- The invalid block(s) information is written the 1st or 2nd page of the
invalid block(s) with 00h data
--->The invalid block(s) status is defined by the 6th byte in the spare
area. Samsung makes sure that either the 1st or 2nd page of every
invalid block has non-FFh data at the column address of 517.
2. Changed SE pin description
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
0.5 1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets July 23th 2001
ready for any command sequences
~ 2.5V
~ 2.5V
VCC
High
WP
WE
1µ
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 150ns --> 20ns
4. #40 Pin Name : nSE --> GND
Remark
Advance
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html.
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
1 page  
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to standby
mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming.
SE is recommended to be coupled to GND or Vcc and should not be toggled during reading or programming.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
Power Line(VCC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.
5
5 Page 
K9F3208W0A-TCB0, K9F3208W0A-TIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
{1st
(n-1)th
nth
(page)
Block A
an error occurs.
{1st
(n-1)th
nth
(page)
Block B
2
Buffer memory of the controller.
1
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet K9F4008W0A-TCB0.PDF ] | |
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