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PDF K9F2808U0M- Data sheet ( Hoja de datos )
| Número de pieza | K9F2808U0M- | |
| Descripción | 16M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
Document Title
16M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 1. Changed tPROG Parameter : 1ms(Max.) → 500µs(Max.)
2. Changed tBERS Parameter : 4ms(Max.) → 3ms(Max.)
3. Changed Input and Output Timing Level 0.8V and 2.0V → 1.5V
1.1 1. Changed tR Parameter : 7µs(Max.) → 10µs(Max.)
2. Changed Nop : 10 cycles(Max.) → Main Array 2 cycles(Max.)
Spare Array 3 cycles(Max.)
3. Added CE don’t care mode during the data-loading and reading
1.2 1. Revised real-time map-out algorithm(refer to technical notes)
1.3 1. Changed device name
- KM29U128T -> K9F2808U0M-YCB0
- KM29U128IT -> K9F2808U0M-YIB0
1.4 1. Changed SE pin description
- SE is recommended to coupled to GND or Vcc and should not be
toggled during reading or programming.
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
Remark
Preliminary
Final
April 10th 1999
Final
June 30th 1999
Sep. 15th 1999
Final
Final
July 17th 2000
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
Spare Area Enable(SE)
The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming.
SE is recommended to be coupled to GND or Vcc and should not be toggled during reading or programming.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
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K9F2808U0M-YCB0, K9F2808U0M-YIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00H
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
I/O 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
I/O 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Page a
Block A
When the error happens with page "a" of Block "A", try
to write the data into another Block "B" from an exter-
nal buffer. Then, prevent further system access to
Block "A" (by creating a "invalid block" table or other
appropriate scheme.)
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Block B
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet K9F2808U0M-.PDF ] | |
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| K9F2808U0M-YCB0 | 16M x 8 Bit NAND Flash Memory | Samsung semiconductor |
| K9F2808U0M-YIB0 | 16M x 8 Bit NAND Flash Memory | Samsung semiconductor |
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