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PDF K9F1608W0A-TIB0 Data sheet ( Hoja de datos )

Número de pieza K9F1608W0A-TIB0
Descripción 2M x 8 Bit NAND Flash Memory
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K9F1608W0A-TIB0 Hoja de datos, Descripción, Manual

K9F1608W0A-TCB0, K9F1608W0A-TIB0
Document Title
2M x 8 Bit NAND Flash Memory
Revision History
Revision No. History
0.0 Initial issue.
1.0 Data Sheet 1998.
1.1 Data Sheet 1999.
1) Added CE dont’ care mode during the data-loading and reading
1.2 1) Revised real-time map-out algorithm(refer to technical notes)
1.3 Changed device name
- KM29W16000AT -> K9F1608W0A-TCB0
- KM29W16000AIT -> K9F1608W0A-TIB0
FLASH MEMORY
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
Remark
Preliminary
Final
Final
July 23th 1999
Sep.15th 1999
Final
Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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K9F1608W0A-TIB0 pdf
K9F1608W0A-TCB0, K9F1608W0A-TIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O 0 ~ I/O 7
The I/O pins are used to input command, address and data, and to outputs data during read operations. The I/O pins float to high-z
when the chip is deselected or the outputs are disabled.
Write Protect (WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and return to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is
deselected or outputs are disabled.
Power Line(VCC & VCCQ)
The VCCQ is the power supply for I/O interface logic. It is electrically isolated from main power line(VCC=2.7~5.5V) for supporting 5V
tolerant I/O with 5V power supply at VCCQ.
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K9F1608W0A-TIB0 arduino
K9F1608W0A-TCB0, K9F1608W0A-TIB0
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60H
Write 00H
Write Block Address
Write Address
Write D0H
Read Data
Write 70H
ECC Generation
SR. 6 = 1 ?
or R/B = 1 ?
No
* No
Erase Error
Yes
SR. 0 = 0 ?
Yes
Erase Completed
No
Reclaim the Error
Verify ECC
Yes
Page Read Completed
* : If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
Buffer
memory
error occurs
Block A
When the error happens in Block "A", try to write the
data into another Block "B" by reloading from an exter-
nal buffer. Then, prevent further system access to
Block "A"(by creating a "invalid block" table or other
appropriate scheme.)
Block B
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