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PDF K7R323684M Data sheet ( Hoja de datos )

Número de pieza K7R323684M
Descripción 1Mx36 & 2Mx18 QDRTM II b4 SRAM
Fabricantes Samsung semiconductor 
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K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Document Title
1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Pin name change from DLL to Doff.
2. Vddq range change from 1.5V to 1.5V~1.8V.
3. Update JTAG test conditions.
4. Reserved pin for high density name change from NC to Vss/SA
5. Delete AC test condition about Clock Input timing Reference Level
6. Delete clock description on page 2 and add HSTL I/O comment
0.2 1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
0.3 1. Add 4Mx9 Organization.
2. Add -FC25 part (Part Number, Idd, AC Characteristics)
3. Add AC electrical characteristics.
4. Change AC timing characteristics.
5. Change DC electrical characteristics(ISB1)
0.4 1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
0.5 1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
0.6 1. Change the JTAG Block diagram
0.7 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
3. Change the Isb1 current.
0.8 1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1.0 1. Final spec release
2.0 1. Delete the x8 Org. Part
Draft Date
June, 30 2001
Dec. 5 2001
Remark
Advance
Preliminary
July, 29. 2002
Preliminary
Sep. 6. 2002
Preliminary
Oct. 7. 2002
Preliminary
Dec. 16, 2002
Preliminary
Dec. 26, 2002
Mar. 20, 2003
Preliminary
Preliminary
April. 4, 2003
Oct. 31, 2003
Dec. 1, 2003
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Dec. 2003
Rev 2.0

1 page




K7R323684M pdf
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7R320982M(4Mx9)
12 3 4 5678
A C Q VSS/SA* SA W NC K NC R
B NC NC NC SA NC
K BW SA
C NC NC NC VSS SA SA SA VSS
D NC D4 NC VSS VSS VSS VSS VSS
E NC
NC
Q4
VDDQ
VSS
VSS
VSS
V DDQ
F NC
NC
NC VDDQ VDD
VSS
VDD
V DDQ
G NC
D5
Q5
VDDQ
VDD
VSS
VDD
V DDQ
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
V DDQ
J NC
NC
NC VDDQ VDD
VSS
VDD
V DDQ
K NC
NC
NC VDDQ VDD
VSS
VDD
V DDQ
L NC
Q6
D6
VDDQ
VSS
VSS
VSS
V DDQ
M NC NC NC VSS VSS VSS VSS VSS
N NC D7 NC VSS SA SA SA VSS
P NC NC Q7 SA SA C SA SA
R TDO TCK
SA
SA
SA
C
SA SA
Notes: 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW controls write to D0:D8 .
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
D8
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
Q8
TDI
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA
D0-8
Q0-8
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
11M,11J,10E,11C,2D,2G,3L,2N,10P
11L,10J,11E,11B,3E,3G,2L,3P,11P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Address Inputs
Data Inputs
Data Outputs
NOTE
1
W
R
BW
VREF
ZQ
VDD
VDDQ
V SS
TMS
TDI
TCK
TDO
NC
4A Write Control Pin,active when low
8A Read Control Pin,active when low
7B Nybble Write Control Pin,active when low
2H,10H
Input Reference Voltage
11H Output Driver Impedance Control Input
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
10R JTAG Test Mode Select
11R JTAG Test Data Input
2R JTAG Test Clock
1R JTAG Test Data Output
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,11D
1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
10N,11N,1P,2P,9P
No Connect
2
3
Notes: 1. C, C, K or K cannot be set to V R E F voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
- 5 - Dec. 2003
Rev 2.0

5 Page





K7R323684M arduino
K7R323682M
K7R321882M
K7R320982M
1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input High Voltage
SYMBOL
VIH (AC)
MIN
VREF + 0.2
MAX
-
Input Low Voltage
V IL (AC)
- VREF - 0.2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or V IH(DC)
Overershoot Timing
Undershoot Timing
UNIT
V
V
NOTES
1,2
1,2
VDDQ+0.5V
20% tKHKH(MIN)
VIH
VDDQ+0.25V
VDDQ
VIL
VSS
VSS-0.25V
VSS-0.5V
Note: For power-up, V IH VDDQ+0.3V and V DD 1.7V and VDDQ 1.4V t 200ms
OPERATING CONDITIONS (0°C TA 70°C)
PARAMETER
SYMBOL
Supply Voltage
VDD
VDDQ
Reference Voltage
V REF
Ground
VSS
Min
1.7
1.4
0.68
0
20% tKHKH(MIN)
MAX
1.9
1.9
0.95
0
UNIT
V
V
V
V
AC TEST CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High/Low Level
Input Reference Level
Input Rise/Fall Time
Output Timing Reference Level
Symbol
VDD
VDDQ
VIH/VIL
VREF
TR/T F
Note: Parameters are tested with RQ=250
Value
1.7~1.9
1.4~1.9
1.25/0.25
0.75
0.3/0.3
VDDQ /2
Unit
V
V
V
V
ns
V
AC TEST OUTPUT LOAD
VREF 0.75V
VDDQ /2
SRAM
Zo=50
50
250
ZQ
- 11 -
Dec. 2003
Rev 2.0

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