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PDF K7R323682 Data sheet ( Hoja de datos )

Número de pieza K7R323682
Descripción 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K7R323684M
K7R321884M
Document Title
1Mx36-bit, 2Mx18-bit QDRTM II b4 SRAM
1Mx36 & 2Mx18 QDRTM II b4 SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Package dimension modify.
P.20 from 13mmx15mm to 15mmx17mm
0.2 1. Pin name change from DLL to Doff.
2. Vddq range change from 1.5V to 1.5V~1.8V.
3. Update JTAG test conditions.
4. Reserved pin for high density name change from NC to Vss/SA
5. Delete AC test condition about Clock Input timing Reference Level
6. Delete clock description on page 2 and add HSTL I/O comment
0.3 1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
0.4 1. Add -FC25 part(AC Characteristics)
2. Add AC electrical characteristics.
3. Change AC timing characteristics
4. Change DC electrical characteristics(ISB1)
0.5 1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
0.6 1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
0.7 1. Change the JTAG Block diagram
0.8 1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
3. Change the Isb1 current
0.9 1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1.0 1. Final spec release
2.0 1. Delete the x8 Org. part
Draft Date
June 30, 2001
Oct. 20, 2001
Remark
Advance
Advance
Dec. 5, 2001
Preliminary
July, 29. 2002
Preliminary
Sep. 6. 2002
Preliminary
Oct. 7. 2002
Preliminary
Dec. 16, 2002
Preliminary
Dec. 26, 2002
Mar. 20, 2003
Preliminary
Preliminary
April. 4, 2003
Aug. 28, 2003
Dec. 1, 2003
Preliminary
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Dec. 2003
Rev 2.0

1 page




K7R323682 pdf
K7R323684M
K7R321884M
1Mx36 & 2Mx18 QDRTM II b4 SRAM
GENERAL DESCRIPTION
The K7R323684M and K7R321884M are37,748,736-bits QDR(Quad Data Rate)
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7R323684M and 2,097,152 words by 18 bits for K7R321884M.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K , and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address for read and write are latched on alternate rising edges of the input clock K.
Data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.
Any request that attempts to interrupt a burst operation in progress is ignored.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW0 and BW1 ( BW 2 and B W3 ) pins.
Nybble write operation is supported with NW 0 and NW1 pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7R323684M and K7R321884M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit or 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
The process continues until all four data are transfered.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the R is disabled after a read operation,the K7R323684M and K7R321884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
- 5 - Dec. 2003
Rev 2.0

5 Page





K7R323682 arduino
K7R323684M
K7R321884M
1Mx36 & 2Mx18 QDRTM II b4 SRAM
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K, C, C)
tKHKL
Clock Low Time (K, K, C, C)
tKLKH
Clock to Clock (K↑ → K, C↑ → C)
tKHKH
Clock to data clock (K ↑ → C, K↑→ C) tKHCH
DLL Lock Time (K, C)
tKC lock
K Static to DLL reset
tKC reset
Output Times
C, C High to Output Valid
tCHQV
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
tAVKH
Control inputs valid to K rising edge
tIVKH
Data-in valid to K, K rising edge
tDVKH
Hold Times
K rising edge to address hold
tKHAX
K rising edge to control inputs hold
tKHIX
K, K rising edge to data-in hold
tKHDX
-25
MIN MAX
4.00
1.60
1.60
1.80
0.00
1024
30
6.30
0.20
1.80
-0.45
-0.45
-0.30
-0.45
0.45
0.45
0.30
0.45
0.50
0.50
0.35
0.50
0.50
0.35
-20
MIN MAX
5.00
2.00
2.00
2.20
0.00
1024
30
7.88
0.20
2.30
-0.45
-0.45
-0.35
-0.45
0.45
0.45
0.35
0.45
0.60
0.60
0.40
0.60
0.60
0.40
-16
UNITS NOTES
MIN MAX
6.00
2.40
2.40
2.70
0.00
1024
30
8.40
0.20
2.80
ns
ns
ns
ns
ns
ns
cycle
ns
5
6
-0.50
-0.50
-0.40
-0.50
0.50
0.50
0.40
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
0.70
0.70
0.50
ns
ns 2
ns
0.70
0.70
0.50
ns
ns 2
ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signal are R and W.
In case of BW0,BW1 (BW2, BW3, also for x36) signal follow the data setup/hold times.
3. If C,C are tied high, K, K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0 °C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70 °C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
- 11 -
Dec. 2003
Rev 2.0

11 Page







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