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PDF K7P403622B Data sheet ( Hoja de datos )

Número de pieza K7P403622B
Descripción 128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Fabricantes Samsung semiconductor 
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K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
Document Title
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Revision History
Rev. No. History
Rev. 0.0
- Preliminary specification release
Rev. 0.1
- Change specification format.
No change was made in parameters.
Rev. 0.2
Rev. 1.0
- Updated IDD, ISB and Input High Level.
Updated tKHKL, tKLKH, tKHQX, tKHQX1 and AC Test Conditions.
For JTAG, updated Vendor Definition and added tSVCH/tCHSX.
- Final specification release
Draft Date Remark
Preliminary
April, 1997
Preliminary
Jan. 1998
Preliminary
Dec. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Dec. 1998
Rev 1.0

1 page




K7P403622B pdf
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit Note
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.9
V
Output Supply Voltage Relative to VSS
VDDQ
VDD
V
Voltage on any I/O pin Relative to VSS
VTERM
-0.5 to VDD+0.5
V
Maximum Power Dissipation
PD 3 W
Output Short-Circuit Current
IOUT
25 mA
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature
TSTG
-55 to 125
°C
NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Core Power Supply Voltage
VDD 3.15
Output Power Supply Voltage
VDDQ
2.35
Input High Level
VIH 1.7
Input Low Level
VIL -0.3
PECL Clock Input High Level
VIH-PECL
2.135
PECL Clock Input Low Level
VIL-PECL
1.490
Operating Junction Temperature
TJ 10
Typ Max Unit
3.3 3.45
V
2.5 3.45
V
-
VDD+0.3
V
- 0.7 V
- 2.420 V
- 1.825 V
- 110 °C
Note
DC CHARACTERISTICS
Parameter
Average Power Supply Operating Current-x36
(VIN=VIH or VIL, ZZ & SS=VIL)
Average Power Supply Operating Current-x18
(VIN=VIH or VIL, ZZ & SS=VIL)
Power Supply Standby Current
(VIN=VIH or VIL, ZZ=VIH)
Input Leakage Current
(VIN=VSS or VDD)
Output Leakage Current
(VOUT=VSS or VDDQ, ZZ=VIH, G=VIH)
Output High Voltage(IOH=-4mA) for VDDQ=3.3V
Output High Voltage(IOH=-4mA) for VDDQ=2.5V
Output Low Voltage(IOL=4mA)
NOTE :1. Minimum cycle. IOUT=0mA.
2. 50% read cycles.
Symbol
IDD5
IDD6
IDD7
IDD5
IDD6
IDD7
ISB
ILI
ILO
VOH1
VOH2
VOL
Min
-
-
-
-1
-1
2.4
2.0
VSS
Max
650
600
550
600
550
500
60
1
1
VDDQ
0.4
Unit
mA
Note
1, 2
mA 1, 2
mA 1
µA
µA
V
V
-5-
Dec. 1998
Rev 1.0

5 Page





K7P403622B arduino
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level
Input Low Level
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
Symbol
VDD
VIH
VIL
VOH
VOL
Min
3.15
2.0
-0.3
2.4
VSS
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
Typ Max Unit
3.3 3.45
V
- VDD+0.3 V
- 0.8 V
-
VDD
V
- 0.4 V
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
Symbol
VIH/VIL
TR/TF
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
3.0/0.0
2.0/2.0
1.5
Min Max
50 -
20 -
20 -
5-
5-
5-
5-
5-
5-
0 10
Unit
V
ns
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
Note
1
Note
JTAG TIMING DIAGRAM
TCK
TMS
TDI
TDO
tCHCH
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tCLQV
- 11 -
tCLCH
Dec. 1998
Rev 1.0

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