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PDF K7N801801B-QC13 Data sheet ( Hoja de datos )

Número de pieza K7N801801B-QC13
Descripción 256Kx36 & 512Kx18-Bit Pipelined NtRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K7N801801B-QC13 Hoja de datos, Descripción, Manual

K7N803601B
K7N801801B
256Kx36 & 512Kx18 Pipelined NtRAMTM
Document Title
256Kx36 & 512Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Add x32 org part and industrial temperature part
0.2 1. change scan order(1) form 4T to 6T at 119BGA(x18)
1.0 1. Final spec release
2. Change ISB2 form 50mA to 60mA
2.0 Change ordering information( remove 225MHz at Nt-Pipelined)
2.1 1. Delete 119BGA package
3.0 1. Remove x32 organization
Draft Date
May. 18. 2001
Aug. 11. 2001
Aug. 28 .2001
Nov. 16. 2001
April. 01. 2002
April. 04. 2003
Nov. 17. 2003
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Nov. 2003
Rev 3.0

1 page




K7N801801B-QC13 pdf
K7N803601B
K7N801801B
PIN CONFIGURATION(TOP VIEW)
256Kx36 & 512Kx18 Pipelined NtRAMTM
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VDD
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N801801B(512Kx18)
80 A10
79 N.C.
78 N.C.
77 VDDQ
76 VSSQ
75 N.C.
74 DQa0
73 DQa1
72 DQa2
71 VSSQ
70 VDDQ
69 DQa3
68 DQa4
67 VSS
66 VDD
65 VDD
64 ZZ
63 DQa5
62 DQa6
61 VDDQ
60 VSSQ
59 DQa7
58 DQa8
57 N.C.
56 N.C.
55 VSSQ
54 VDDQ
53 N.C.
52 N.C.
51 N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
A0 - A18
Address Inputs
ADV
Address Advance/Load
WE Read/Write Control Input
CLK Clock
CKE
Clock Enable
CS1 Chip Select
CS2 Chip Select
CS2 Chip Select
BWx(x=a,b) Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
LBO
Burst Mode Control
32,33,34,35,36,37,44
45,46,47,48,49,50,80
81,82,83,99,100
85
88
89
87
98
97
92
93,94
86
64
31
VDD
VSS
N.C.
DQa0~a8
DQb0~b8
VDDQ
VSSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
TQFP PIN NO.
14,15,16,41,65,66,91
17,40,67,90
1,2,3,6,7,25,28,29,30,
38,39,42,43,51,52,53,
56,57,75,78,79,84,95,96
58,59,62,63,68,69,72,73,74
8,9,12,13,18,19,22,23,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM.
2. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 5 - Nov. 2003
Rev 3.0

5 Page





K7N801801B-QC13 arduino
K7N803601B
K7N801801B
Output Load(A)
Dout
Zo=50
256Kx36 & 512Kx18 Pipelined NtRAMTM
RL=50
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667
353Ω / 1538
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 to 70°C)
PARAMETER
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (WE, BWX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE, BWEX)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
SYMBOL
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tCES
tDS
tWS
tADVS
tCSS
tAH
tCEH
tDH
tWH
tADVH
tCSH
tPDS
tPUS
-16
MIN MAX
6.0 -
- 3.5
- 3.5
1.5 -
1.5 -
0-
- 3.0
- 3.0
2.2 -
2.2 -
1.5 -
1.5 -
1.5 -
1.5 -
1.5 -
1.5 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
2-
2-
-13
MIN MAX
7.5 -
- 4.2
- 4.2
1.5 -
1.5 -
0-
- 3.5
- 3.5
3.0 -
3.0 -
1.5 -
1.5 -
1.5 -
1.5 -
1.5 -
1.5 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
0.5 -
2-
2-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
4. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
5. To avoid bus contention, At a given voltage and temperature tLZC is more than tHZC.
The specs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 11 -
Nov. 2003
Rev 3.0

11 Page







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