DataSheet.es    


PDF K7M321825M-QC75 Data sheet ( Hoja de datos )

Número de pieza K7M321825M-QC75
Descripción 1Mx36 & 2Mx18 Flow-Through NtRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



Hay una vista previa y un enlace de descarga de K7M321825M-QC75 (archivo pdf) en la parte inferior de esta página.


Total 18 Páginas

No Preview Available ! K7M321825M-QC75 Hoja de datos, Descripción, Manual

K7M323625M
K7M321825M
1Mx36 & 2Mx18 Flow-Through NtRAMTM
Document Title
1Mx36 & 2Mx18-Bit Flow Through NtRAMTM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Add 165FBGA package
0.2 1. Update JTAG scan order
0.3 1. Change pin out for 165FBGA
- x18/x36 ; 11B => from A to NC , 2R ==> from NC to A
0.4 1. Insert pin at JTAG scan order of 165FBGA in connection with
pin out change
- x18/x36 ; insert Pin ID of 2R to BIT number of 69
0.5 1. Add Icc, Isb, Isb1 and Isb2 values.
1.0 1. Final datasheet release.
1.1 1. Change the Stand-by current (Isb)
Before After
Isb - 65 : 100 140
- 75 : 90 130
- 85 : 80 130
Isb1 : 90 110
Isb2 : 80 100
2.0 1. Delete the 119BGA and 165FBGA package
2. Delete the 6.5ns and 8.5ns speed bin
Draft Date
May. 10. 2001
Aug. 29. 2001
Dec. 03. 2001
Feb. 14. 2002
Apr. 20. 2002
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
May. 10. 2002
Sep. 26. 2002
Oct. 17. 2003
Preliminary
Final
Final
Nov. 18, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Nov. 2003
Rev 2.0

1 page




K7M321825M-QC75 pdf
K7M323625M
K7M321825M
PIN CONFIGURATION(TOP VIEW)
1Mx36 & 2Mx18 Flow-Through NtRAMTM
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb8
DQb7
VSSQ
VDDQ
DQb6
DQb5
VSS
VDD
VDD
VSS
DQb4
DQb3
VDDQ
VSSQ
DQb2
DQb1
DQb0
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M321825M(2Mx18)
80 A10
79 N.C.
78 N.C.
77 VDDQ
76 VSSQ
75 N.C.
74 DQa0
73 DQa1
72 DQa2
71 VSSQ
70 VDDQ
69 DQa3
68 DQa4
67 VSS
66 VSS
65 VDD
64 ZZ
63 DQa5
62 DQa6
61 VDDQ
60 VSSQ
59 DQa7
58 DQa8
57 N.C.
56 N.C.
55 VSSQ
54 VDDQ
53 N.C.
52 N.C.
51 N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A20
Address Inputs
ADV
Address Advance/Load
WE Read/Write Control Input
CLK
Clock
CKE
Clock Enable
CS1
Chip Select
CS2
Chip Select
CS2
Chip Select
BW x(x=a,b) Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
LBO
Burst Mode Control
32,33,34,35,36,37,43
44,45,46,47,48,49,50,
80,81,82,83,84,99,100
85
88
89
87
98
97
92
93,94
86
64
31
VDD
VSS
N.C.
DQa0~a8
DQb0~b8
VDDQ
VSSQ
Power Supply(+3.3V) 15,16,41,65,91
Ground
14,17,40,66,67,90
No Connect
1,2,3,6,7,25,28,29,30,
38,39,42,51,52,53,
56,57,75,78,79,95,96
Data Inputs/Outputs 58,59,62,63,68,69,72,73,74
Data Inputs/Outputs 8,9,12,13,18,19,22,23,24
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
- 5 - Nov. 2003
Rev 2.0

5 Page





K7M321825M-QC75 arduino
K7M323625M
K7M321825M
Output Load(A)
Dout
Zo=50
1Mx36 & 2Mx18 Flow-Through NtRAMTM
RL=50
30pF*
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319Ω / 1667
353Ω / 1538
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
PARAMETER
SYMBOL
-75
MIN MAX
UNIT
Cycle Time
Clock Access Time
tCYC
tCD
8.5
-
- ns
7.5 ns
Output Enable to Data Valid
tOE -
3.5 ns
Clock High to Output Low-Z
Output Hold from Clock High
tLZC
tOH
2.5
2.5
- ns
- ns
Output Enable Low to Output Low-Z
tLZOE
0
- ns
Output Enable High to Output High-Z
tHZOE
-
3.5 ns
Clock High to Output High-Z
tHZC
-
4.0 ns
Clock High Pulse Width
Clock Low Pulse Width
tCH 2.8
tCL 2.8
- ns
- ns
Address Setup to Clock High
tAS 2.0
- ns
CKE Setup to Clock High
tCES
2.0
- ns
Data Setup to Clock High
tDS 2.0
- ns
Write Setup to Clock High (WE, BWX)
tWS 2.0
- ns
Address Advance Setup to Clock High
tADVS
2.0
- ns
Chip Select Setup to Clock High
tCSS
2.0
- ns
Address Hold from Clock High
CKE Hold from Clock High
tAH
tCEH
0.5
0.5
- ns
- ns
Data Hold from Clock High
tDH 0.5
- ns
Write Hold from Clock High (WE , BW X)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
tWH
tADVH
tCSH
0.5
0.5
0.5
- ns
- ns
- ns
ZZ High to Power Down
tPDS
2
- cycle
ZZ Low to Power Up
tPUS
2
- cycle
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
Both cases must meet setup and hold times.
4. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC.
The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions
(0°C,3.465V) than tH Z C, which is a Max. parameter(worst case at 70°C,3.135V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperatue.
- 11 -
Nov. 2003
Rev 2.0

11 Page







PáginasTotal 18 Páginas
PDF Descargar[ Datasheet K7M321825M-QC75.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
K7M321825M-QC751Mx36 & 2Mx18 Flow-Through NtRAMSamsung semiconductor
Samsung semiconductor
K7M321825M-QC751Mx36 & 2Mx18-Bit Pipelined NtRAMSamsung semiconductor
Samsung semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar