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PDF K7D803671B-HC30 Data sheet ( Hoja de datos )

Número de pieza K7D803671B-HC30
Descripción 256Kx36 & 512Kx18 SRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K7D803671B-HC30 Hoja de datos, Descripción, Manual

K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
Document Title
8M DDR SYNCHRONOUS SRAM
Revision History
Rev No.
History
Rev. 0.0 -Initial document.
Rev. 0.1 -ZQ tolerance changed from 10% to 15%
Rev. 0.2
-Stop Clock Standby Current condition changed from
VIN=VDD-0.2V or 0.2V fixed to VIN=VIH or VIH
Rev. 0.3
-VDDQ Max. changed to 2.0V
SA0, SA1 defined for Boundary Scan Order
Rev. 0.5 -Deleted -HC16 part(Part Number, Idd, AC Characterisctics)
Rev. 0.6
- Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V
Rev. 0.7
- LBO input level changed from High/Low to VDDQ/VSS
- Stop Clock Standby Current condition changed
from K=Low, K=High to K=Low, K=Low
- tCHQV/tCLQV changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- tCHQX/tCLQX changed from -0.3ns to -0.2ns for -33 part
from -0.3ns to -0.2ns for -30 part
from -0.4ns to -0.25ns for -25part
- tCHQZ/tCLQZ changed from 0.1ns to 0.2ns for -33 part
from 0.1ns to 0.2ns for -30 part
from 0.1ns to 0.25ns for -25part
- tKXCH changed from 1.8ns to 1.7ns for -33 part
- tKXCL changed from 1.8ns to 1.7ns for -33 part
Rev. 1.0
- Clarification on the features and the timing waveforms regarding the
burst controllability.
- Recommended DC operating conditions for Clock added.
- AC test conditions for VDDQ=1.8V and Single ended clock added.
(AC Test Conditions 2)
- Package thermal characteristics added.
Rev. 2.0 - Add-HC35 part(Part Number, Idd, AC Characteristics)
Rev. 3.0
- Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V
- VCM-CLK Min changed from 0.6V to 0.68V
Rev. 4.0 - Add-HC37 part(Part Number, Idd, AC Characteristics)
DraftData
July. 2000
Aug. 2000
Oct. 2000
Nov. 2000
Jan. 2001
Feb. 2001
Mar. 2001
Remark
Advance
Advance
Advance
Advance
Prelimary
Prelimary
Prelimary
May. 2001
Final
Sep. 2001
Jan. 2002
Jan. 2002
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
January. 2002
Rev 4.0

1 page




K7D803671B-HC30 pdf
K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
TRUTH TABLE
K G B1 B2 B3 DQ
Operation
L X X X X Hi-Z
X H L X Hi-Z
L L H H DOUT
L L H L DOUT
X L L H DIN
X L L L DIN
XHHXB
Clock Stop
No Operation, Pipeline High-Z
Load Address, Single Read
Load Address, Double Read
Load Address, Single Write
Load Address, Double Write
Increment Address, Continue
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
- K & K are complementary.
BURST SEQUENCE TABLE
4 Burst Operation for Interleaved Burst (LBO = VDDQ)
Interleaved Burst
Case 1
Case 2
A1 A0 A1 A0
First Address
0 001
0 100
1 011
Fourth Address 1 1 1 0
Case 3
A1 A0
10
11
00
01
NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V.
4 Burst Operation for Linear Burst (LBO = VSS)
Linear Burst Mode
Case 1
A1 A0
First Address
00
01
10
Fourth Address 1 1
Case 2
A1 A0
01
10
11
00
Case 3
A1 A0
10
11
00
01
Case 4
A1 A0
11
10
01
00
Case 4
A1 A0
11
00
01
10
-5-
January. 2002
Rev 4.0

5 Page





K7D803671B-HC30 arduino
K7D803671B
K7D801871B
256Kx36 & 512Kx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
NOP
READ
READ
READ CONTINUE READ CONTINUE READ
NOP
(burst of 4)
(burst of 4)
(burst of 2)
NOP
WRITE
READ
WRITE CONTINUE READ CONTINUE
(burst of 4)
(burst of 4)
12
34
5
6
7
89
10 11 12
K
tKHKH
K
B1
B2
tBVKH
B3
tKHBX
SA A0
tAVKH
tKHAX
G
DQ QX2
A5 A1
A2 A3
tGHQX
tGHQZ
Q01 Q02 Q03 Q04 Q51 Q52 Q53 Q54 Q11 Q12
tKHDX
tDVKH
tGLQV
tGLQX
D21 D22 D23 D24
Q31
tCHQZ
CQ
CQ
tKXCH tCHQV
tCHLZ
tCHQX
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
- 11
January. 2002
Rev 4.0

11 Page







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