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PDF K6X4016C3F-TF70 Data sheet ( Hoja de datos )

Número de pieza K6X4016C3F-TF70
Descripción 256Kx16 bit Low Power full CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6X4016C3F-TF70 Hoja de datos, Descripción, Manual

K6X4016C3F Family
Document Title
256Kx16 bit Low Power full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial draft
0.1 Revised
Added Commercial Product.
Deleted 44-TSOP2-400R Package Type.
1.0 Finalized
- Changed ICC from 10mA to 5mA
- Changed ICC1 from 10mA to 7mA
- Changed ICC2 from 50mA to 30mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(Commercial) from 15µA to 12µA
- Changed IDR(industrial) from 20µA to 12µA
- Changed IDR(Automotive) from 30µA to 25µA
CMOS SRAM
Draft Date
July 26, 2002
Remark
Preliminary
November 29, 2002 Preliminary
September 16, 2003 final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
September 2003

1 page




K6X4016C3F-TF70 pdf
K6X4016C3F Family
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL=100pF+1TTL
CL=50pF+1TTL
CMOS SRAM
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
( Vcc=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C, Automotive Product : TA=-40 to 125°C, )
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Chip disable to high-Z output
OE disable to high-Z output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tBLZ
tHZ
tOHZ
tOH
tBA
tBHZ
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
tBW
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5 -
5-5 -
0 20 0 25
0 20 0 25
10 - 10 -
- 25 - 35
0 20 0 25
55 - 70 -
45 - 60 -
0-0 -
45 - 60 -
45 - 55 -
0-0 -
0 20 0 25
25 - 30 -
0-0 -
5-5 -
45 - 60 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
Test Condition
VDR CSVcc-0.2V
K6X4016C3F-B
IDR Vcc=3.0V, CSVcc-0.2V K6X4016C3F-F
K6X4016C3F-Q
tSDR
tRDR
See data retention waveform
Min
2.0
0
5
Typ
-
-
-
-
Max
5.5
12
12
25
-
-
Unit
V
µA
ms
5 Revision 1.0
September 2003

5 Page










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