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PDF K6X1008T2D-BF55 Data sheet ( Hoja de datos )

Número de pieza K6X1008T2D-BF55
Descripción 128Kx8 bit Low Power CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6X1008T2D-BF55 Hoja de datos, Descripción, Manual

K6X1008T2D Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial draft
Draft Data
July 15, 2002
Remark
Preliminary
0.1 Revised
December 4, 2002
Preliminary
- Deleted 32-TSOP1-0820R, 32-TSOP1-0813.4F/R Package Type.
- Added Commercial product.
- Added 55ns product( Vcc = 3.0V~3.6V)
0.2 Revised
- Added Lead Free 32-SOP-525 Product
- Added Lead Free 32-TSOP1-0820F Product
June 23, 2003
Preliminary
1.0 Finalized
- Changed ICC from 3mA to 2mA
- Changed ICC2 from 25mA to 20mA
- Changed ISB1(Commercial) from 10µA to 6µA
- Changed ISB1(industrial) from 10µA to 6µA
- Changed ISB1(Automotive) from 20µA to 10µA
- Changed IDR(Commercial) from 10µA to 6µA
- Changed IDR(industrial) from 10µA to 6µA
- Changed IDR(Automotive) from 20µA to 10µA
September 16, 2003 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
September 2003

1 page




K6X1008T2D-BF55 pdf
K6X1008T2D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS
(VCC=2.7~3.6V, Commercial product:TA=0 to 70°C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C )
Parameter List
Symbol
55ns1)
Min Max
Speed Bins
70ns
Min Max
85ns
Min Max
Units
Read Cycle Time
tRC
Address Access Time
tAA
Chip Select to Output
tCO
Read
Output Enable to Valid Output
Chip Select to Low-Z Output
tOE
tLZ
Output Enable to Low-Z Output
tOLZ
Chip Disable to High-Z Output
tHZ
Output Disable to High-Z Output
tOHZ
Output Hold from Address Change
tOH
Write Cycle Time
tWC
Chip Select to End of Write
tCW
Address Set-up Time
tAS
Address Valid to End of Write
tAW
Write
Write Pulse Width
Write Recovery Time
tWP
tWR
Write to Output High-Z
tWHZ
Data to Write Time Overlap
tDW
Data Hold from Write Time
tDH
End Write to Output Low-Z
tOW
1. Voltage range is 3.0V~3.6V for commercial and industrial product.
55 - 70 - 85 -
- 55 - 70 - 85
- 55 - 70 - 85
- 25 - 35 - 40
10 - 10 - 10 -
5-5-5-
0 25 0 25 0 25
0 25 0 25 0 25
10 - 10 - 15 -
55 - 70 - 85 -
45 - 60 - 70 -
0-0-0-
45 - 60 - 70 -
40 - 50 - 60 -
0-0-0-
0 25 0 25 0 30
20 - 25 - 35 -
0-0-0-
5-5-5-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
Test Condition
Min Typ Max Unit
VDR CS1Vcc-0.2V1)
IDR Vcc=3.0V, CS1Vcc-0.2V1)
2.0 - 3.6 V
K6X1008T2D-B - - 6 µA
K6X1008T2D-F - - 6 µA
K6X1008T2D-Q
10 µA
tSDR
tRDR
See data retention waveform
0 - - ms
5- -
1. CS1Vcc-0.2V, CS2VCC-0.2V, or CS20.2V
5 Revision 1.0
September 2003

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