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PDF K6T4016U3C-F Data sheet ( Hoja de datos )

Número de pieza K6T4016U3C-F
Descripción 256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6T4016U3C-F Hoja de datos, Descripción, Manual

K6T4016V3C, K6T4016U3C Family
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No History
0.0 Initial draft
0.1 Revise
- Speed bin change
Commercial: 70/85ns to 70/85/100ns
Industrial: 85/100ns to 70/85/100ns
- DC Characteristics change
ICC: 5mA at read/write to 4mA at read
ICC1: 5mA to 6mA
ICC2: 50mA to 45mA
ISB: 0.5mA to 0.3mA
ISB1: 10µA to 15µA for commercial parts
0.11 Errata correction
1.0 Finalize
2.0 Revise
- Add K6T4016V3C-TB55 product
2.01
Revise
- Improved VOH(output high voltage) from 2.2V to 2.4V.
Draft Date
January 13, 1998
June 12, 1998
Remark
Advance
Preliminary
August 13, 1998
November 16, 1998
June 26, 2001
Final
Final
October 15, 2001
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 2.01
October 2001

1 page




K6T4016U3C-F pdf
K6T4016V3C, K6T4016U3C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL1)
1.Including scope and jig capacitance
AC CHARACTERISTICS (K6T4016V3C Family: Vcc=3.0~3.6V, K6T4016U3C Family: Vcc=2.7~3.3V
Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
LB, UB valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
LB, UB disable to high-Z output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
Symbol
tRC
tAA
tCO
tOE
tBA
tLZ
tOLZ
tBLZ
tOH
tHZ
tOHZ
tBHZ
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
tBW
55ns
Min Max
55 -
- 55
- 55
- 25
- 25
10 -
5-
5-
10 -
0 20
0 20
0 20
55 -
45 -
0-
45 -
40 -
0-
0 20
25 -
0-
5-
45 -
Speed Bins
70ns
85ns
Min Max Min Max
70 - 85 -
- 70 - 85
- 70 - 85
- 35 - 40
- 35 - 40
10 - 10 -
5-5 -
5-5 -
10 - 10 -
0 25 0 25
0 25 0 25
0 25 0 25
70 - 85 -
60 - 70 -
0-0 -
60 - 70 -
55 - 60 -
0-0 -
0 25 0 25
30 - 35 -
0-0 -
5-5 -
60 - 70 -
100ns
Min Max
100 -
- 100
- 100
- 50
- 50
10 -
5-
5-
15 -
0 30
0 30
0 30
100 -
80 -
0-
80 -
70 -
0-
0 30
40 -
0-
5-
80 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR CSVcc-0.2V
Data retention current
IDR Vcc=3.0V, CSVcc-0.2V
Data retention set-up time
Recovery time
1. Industrial product = 20µA
tSDR
tRDR
See data retention waveform
Min Typ Max Unit
2.0 - 3.6 V
- 0.5 151) µA
0- -
ms
5- -
5 Revision 2.01
October 2001

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