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PDF K6T4008U1C-MB70 Data sheet ( Hoja de datos )

Número de pieza K6T4008U1C-MB70
Descripción 512Kx8 bit Low Power and Low Voltage CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6T4008U1C-MB70 Hoja de datos, Descripción, Manual

K6T4008V1C, K6T4008U1C Family
Document Title
512Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0 Initial Draft
0.1 Revisied
- Speed bin change
KM68U4000C : 85/100ns 70/85/100ns
- DC Characteristics change
ICC : 5mA at read/write 4mA at read
ICC1 : 3mA 4mA
ICC2 : 35mA 30mA
ISB : 0.5mA 0.3mA
ISB1 : 10µA 15µA for commercial parts
- Add 32-TSOP1-0820
0.11 Errata correct
- 32-TSOP1-0813 products: T TG
1.0 Finalize
Draft Data
January 13, 1998
June 12, 1998
Remark
Advance
Preliminary
November 7, 1998
January 15, 1999
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 1.0
January 1999

1 page




K6T4008U1C-MB70 pdf
K6T4008V1C, K6T4008U1C Family
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL1)=30pF+1TTL
1. 70ns product
CMOS SRAM
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V
Commercial product:: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
70ns
85ns
100ns
Min Max Min Max Min Max
Read cycle time
tRC 70 - 85 - 100 -
Address access time
tAA - 70 - 85 - 100
Chip select to output
tCO - 70 - 85 - 100
Output enable to valid output
tOE - 35 - 40 - 50
Read Chip select to low-Z output
tLZ 10 - 10 - 10 -
Output enable to low-Z output
tOLZ 5 - 5 - 5 -
Chip disable to high-Z output
tHZ 0 25 0 25 0 30
Output disable to high-Z output
tOHZ
0 25 0 25 0 30
Output hold from address change
tOH 10 - 10 - 15 -
Write cycle time
tWC 70 - 85 - 100 -
Chip select to end of write
tCW 60 - 70 - 80 -
Address set-up time
tAS 0 - 0 - 0 -
Address valid to end of write
tAW 60 - 70 - 80 -
Write pulse width
Write
Write recovery time
tWP 55 - 55 - 70 -
tWR 0 - 0 - 0 -
Write to output high-Z
tWHZ
0 25 0 25 0 30
Data to write time overlap
tDW 30 - 35 - 40 -
Data hold from write time
tDH 0 - 0 - 0 -
End write to output low-Z
tOW 5 - 5 - 5 -
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR CSVcc-0.2V
Data retention current
IDR Vcc=3.0V, CSVcc-0.2V
Data retention set-up time
Recovery time
1. Industrial product = 20µA
tSDR
tRDR
See data retention waveform
Min Typ Max Unit
2.0 - 3.6 V
- 0.5 151) µA
0- -
ms
5- -
5 Revision 1.0
January 1999

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