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PDF K6T1008C2E-TB55 Data sheet ( Hoja de datos )

Número de pieza K6T1008C2E-TB55
Descripción 128Kx8 bit Low Power CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K6T1008C2E Family
Document Title
128Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No. History
0.0 Design target
1.0 Finalize
- Improve tWP form 55ns to 50ns for 70ns product.
- Remove 55ns speed bin from industrial product.
1.01
Errata correction
2.0 Revise
3.0 Revise
- Add 55ns parts to industrial products.
CMOS SRAM
Draft Data
October 12, 1998
August 30, 1999
Remark
Preliminary
Final
December 1, 1999
February 14, 2000
March 3, 2000
Final
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 3.0
March 2000

1 page




K6T1008C2E-TB55 pdf
K6T1008C2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)
Parameter List
Read
Write
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 25
20 - 25 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min Typ Max Unit
Vcc for data retention
VDR CS1Vcc-0.2V1)
2.0 - 5.5 V
K6T1008C2E-L -
- 20
Data retention current
IDR Vcc=3.0V, CS1Vcc-0.2V1)
K6T1008C2E-B
K6T1008C2E-P
-
-
- 10 µA
- 25
K6T1008C2F-F -
- 10
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
0 - - ms
5- -
1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or CS20.2V(CS2 controlled)
5 Revision 3.0
March 2000

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