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PDF K6T0808C1D-DB55 Data sheet ( Hoja de datos )

Número de pieza K6T0808C1D-DB55
Descripción 32Kx8 bit Low Power CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! K6T0808C1D-DB55 Hoja de datos, Descripción, Manual

K6T0808C1D Family
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No History
0.0 Initial draft
0.1 First revision
- KM62256DL/DLI ISB1 = 100 50µA
KM62256DL-L ISB1 = 20 10µA
KM62256DLI-L ISB1 = 50 15µA
- CIN = 6 8pF, CIO = 8 10pF
- KM62256D-4/5/7 Family
tOH = 5 10ns
- KM62256DL/DLI IDR = 5030µA
KM62256DL-L/DLI-L IDR = 30 15µA
1.0 Finalize
- Remove ICC write value
- Improved operating current
ICC2 = 70 60mA
- Improved standby current
KM62256DL/DLI ISB1 = 50 30µA
KM62256DL-L ISB1 = 10 5µA
KM62256DLI-L ISB1 = 15 5µA
- Improved data retention current
KM62256DL/DLI IDR = 30 5µA
KM62256DL-L/DLI-L IDR = 15 3µA
- Remove 45ns part from commercial product and 100ns part
from industrial product.
Replace test load 100pF to 50pF for 55ns part
CMOS SRAM
Draft Data
May 18, 1997
April 1, 1997
Remark
Design target
Preliminily
November 11, 1997 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
November 1997

1 page




K6T0808C1D-DB55 pdf
K6T0808C1D Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)
Parameter List
Read cycle time
Address access time
Chip select to output
Read
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
1. The parameter is tested with 50pF test load.
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
551)ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 30
0 20 0 30
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 25
25 - 30 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
Test Condition
Min Typ Max Unit
VDR CSVcc-0.2V
2.0 - 5.5 V
IDR Vcc=3.0V, CSVcc-0.2V
L-Ver
LL-Ver
-
-
1 15 µA
0.2 3
tSDR
tRDR
See data retention waveform
0 - - ms
5- -
Revision 1.0
November 1997

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