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PDF K6R1008C1C-I15 Data sheet ( Hoja de datos )
| Número de pieza | K6R1008C1C-I15 | |
| Descripción | 128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges. | |
| Fabricantes | Samsung semiconductor | |
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Hay una vista previa y un enlace de descarga de K6R1008C1C-I15 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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PRELIMINARY
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev.No.
History
Rev. 0.0
Initial release with Preliminary.
Draft Data
Aug. 5. 1998
Remark
Preliminary
Rev. 1.0
Rev. 2.0
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Add 10ns part.
Mar. 3. 1999
Final
Mar. 3. 2000
Final
Rev. 3.0
Delete 20ns speed bin
Sep. 24. 2001
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 3.0
September 2001
1 page  
K6R1008C1C-C/C-L, K6R1008C1C-I/C-P
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
K6R1008C1C-10
Min Max
10 -
7-
0-
7-
7-
10 -
0-
05
5-
0-
3-
* The above parameters are also guaranteed at industrial temperature range.
K6R1008C1C-12
Min Max
12 -
8-
0-
8-
8-
12 -
0-
06
6-
0-
3-
PRELIMINARY
CMOS SRAM
K6R1008C1C-15
Min Max
15 -
9-
0-
9-
9-
15 -
0-
07
7-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
Valid Data
tOHZ
tOH
tPD
50%
-5-
Revision 3.0
September 2001
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet K6R1008C1C-I15.PDF ] | |
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